Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-03-27
2003-06-03
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090, C324S759030
Reexamination Certificate
active
06573743
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a testing apparatus and a method for performing an electrical characteristic test for a test piece, particularly, to a testing apparatus and a method for performing an electrical characteristic test, e.g., a reliability test such as a burn-in test, for an electronic part having a large number of electronic circuits formed on the surface. To be more specific, the present invention relates to a wafer collective testing apparatus and a method for applying a reliability test such as a burn-in test, which is applied to a plurality of semiconductor devices, i.e., an IC chip, to an IC chip as formed on a semiconductor wafer. The present invention also relates to a contactor used for testing the electrical characteristics of a test piece and a method of manufacturing the same, more particularly, to a contactor that is collectively brought into contact with the test piece in performing the test and a method of manufacturing the same.
The electrical characteristics of each of a large number of IC chips formed on the surface of a wafer are tested in a process of testing a semiconductor device. IC chips free from defects are screened on the basis of the test results. The screened good IC chips are packaged with a synthetic resin or a ceramic material in the assembling process. In a burn-in test that is one of reliability tests, thermal and electrical stresses are applied to the packaged IC chip to make the latent defects of the IC chip visible.
With progress in miniaturization and required performance of various electrical appliances, the IC chip is also miniaturized and the degree of integration of the IC chip is promoted. Also, with progress in the operating speed of the electrical appliances, high frequency characteristics of 100 MHz to 300 MHz are required in the logic circuit or the memory circuit.
Recently, various mounting techniques have been developed for further miniaturization of the semiconductor device. Particularly, a technique in which an IC chip is not packaged, e.g., a flip chip mounting technique in which a so-called bare chip is mounted to an electrical appliance, is being developed. As a result of development of the particular technique, a quality-guaranteed KGD has come to be put on the market. In this case, the quality as KGD must be guaranteed by applying a burn-in test (reliability test) as a final test to each IC chip.
A technique for testing the reliability of an IC chip as formed on a wafer is proposed in, for example, Japanese Patent Disclosure (Kokai) No. 7-231019, Japanese Patent Disclosure No. 8-5666 and Japanese Patent Disclosure No. 8-340030. Particularly, the former two prior arts propose a technique for collectively bringing a wafer into contact with a contactor without fail while eliminating the thermal effect in performing a reliability test. In testing the reliability of the IC chip as formed on a wafer surface, it is very important to bring collectively the wafer into contact with a contactor at a high accuracy under high temperatures in order to ensure reliability of the burn-in test.
A probe card is used as a contactor in testing the electrical characteristics of an IC chip having a large number of memory circuits, logic circuits, etc. formed on a wafer. The probe card includes a plurality of probe terminals arranged to correspond to, for example, the positions of a plurality of electrode pads formed on the IC chip. During the test, the probe terminals of the probe card are electrically brought into contact with the electrode pads to play the role of relaying the testing signal and information on the result of the test between a tester and the IC chip. The probe terminal is formed of, for example, a tungsten wire or a pogo pin.
Recently, the number of electrode pads is rapidly increased with improvement in the degree of integration of IC chips. As a result, the pitch of arranging the electrode pads becomes narrower and narrower. Naturally, the number of probe terminals of the probe card is also increased rapidly, with the result that the probe terminals are arranged at a smaller pitch.
However, in a conventional wafer collective testing apparatus used for the reliability test, a long electrical connecting wire is used for connecting a pattern signal generating circuit mounted to the tester to the contactor. However, the pattern signal for the testing generated from the pattern signal generating circuit is electrically affected while transmitted through the long connecting wire, making it very difficult to test the reliability of the high speed IC chip under the actual operating speed. Therefore, in the conventional reliability test, it was necessary to test the reliability at an operating speed, e.g., about 1 to 10 MHz, at which the electrical influence is not given by the connecting wire.
Concerning the contactor, a plurality of probe terminals are manually mounted to a substrate. It should be noted in this connection that the number of probe terminals is increased nowadays as described previously, making it difficult to align manually the positions for mounting very small probe terminals at a small pitch and to mount manually the probe terminals. It follows that it is difficult to manufacture the contactor itself. In addition, the probe terminal made of a tungsten wire involves a limitation in the mounting structure, making it difficult to arrange the probe terminals to correspond flexibly to the arrangement of the testing electrode pads for the test piece. Incidentally, a technique relating to a contactor having probe terminals arranged at a small pitch is disclosed in, for example, Japanese Patent Disclosure No. 5-198636, Japanese Patent Disclosure No. 5-218156 or Japanese Patent Disclosure No. 10-38918.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to solve the above-noted problems inherent in the conventional technique.
To be more specific, the present invention is intended to provide a collective testing apparatus for a test piece and a testing method, which permit conducting a test for electrical characteristics, i.e., a reliability test, of a test piece under an actual operating speed without receiving electrical influences given by the connecting wiring between a tester and a contactor even if the test piece operates at a high speed.
The present invention is also intended to provide a contactor, which can be made to correspond flexibly to the arrangement of the testing electrode pads of a test piece, which permits automatically mounting the probe terminals, and which also permits the probe terminals to be brought into contact satisfactorily with the electrode pads of the test piece so as to improve the accuracy of the test, and to provide a method of manufacturing the contactor.
According to a first aspect of the present invention, there is provided a testing apparatus for testing the electric characteristics of a plurality of circuit elements formed on a test piece, comprising:
a chuck for supporting a test piece having a plurality of test electrodes formed on the surface;
a tester for generating a control signal relating to an electrical characteristic test of a plurality of circuit elements formed on the test piece and for testing the electrical characteristics of the circuit elements based on the test result information generated from the circuit elements; and
a contactor including a plurality of probe terminals that are collectively brought into contact with at least some of the test electrodes, a test pattern signal generating circuit for generating a test pattern signal in accordance with the control signal transmitted from the tester, a first electric connection wiring arranged between the test pattern signal generating circuit and the probes for transmitting the test pattern signal generated from the test pattern signal generating circuit to the probes, and second electric connection wirings for outputting the test result information generated from the circuit elements to the tester via the probe terminals.
In the testing apparatus of this embodi
Cuneo Kamand
Tang Minh N.
Tokyo Electron Limited
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