Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Fusible link or intentional destruct circuit
Reexamination Certificate
2002-07-08
2003-10-14
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Fusible link or intentional destruct circuit
C327S416000
Reexamination Certificate
active
06633196
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to integrated circuit dice and, in particular, to devices and methods for limiting the extent to which circuits in integrated circuit dice load bond pads and other circuit nodes in the dice.
2. State of the Art
Integrated circuit (IC) dice or “chips” are small, generally rectangular electronic devices cut from a semiconductor wafer, such as a silicon wafer, on which multiple ICs have been fabricated. IC dice generally communicate with external circuitry, such as other IC dice, through wire, or tape-automated-bonding (TAB), leads connecting bond pads on the dice to the external circuitry, as shown in U.S. Pat. Nos. 5,252,853 and 5,272,590.
In most IC dice, including Dynamic Random Access Memory (DRAM) IC dice, it is preferable that electronic signals between external circuitry and circuitry on the dice propagate into or out of the dice through the bond pads as quickly as possible. For example, in DRAM IC dice it is preferable that address signals propagate into the dice through the bond pads as quickly as possible, because time spent waiting for the address signals to propagate into the dice slows the response time of the dice to read and write requests.
It is recognized that, in some IC dice, including some DRAM IC dice, there are anomalous differences in the time it takes electronic signals to propagate into or out of similar bond pads on the dice. For example, in the D37M DRAM IC die manufactured by the Assignee of the present invention, Micron Technology, Inc. of Boise, Id., address signals take 1 ns longer to propagate into one address bit bond pad (A9) than any other address bit bond pad. As a result, the response time of the D37M DRAM IC die is slowed by at least 1 ns.
Since it is preferable for electronic signals to propagate into and out of IC dice as quickly as possible, there is a need in the art for a recognition of the reason for the anomalous differences in propagation time described above. There is also a need for a device and method for reducing these anomalous differences in IC dice.
SUMMARY OF THE INVENTION
The present invention recognizes that anomalous differences in the time it takes electronic signals to propagate into or out of similar bond pads on some integrated circuit (IC) dice are caused by extra circuitry in the IC dice electrically loading some of the similar bond pads but not others. For example, some IC dice include different input buffers connected to the same bond pad, and in different configurations of the IC dice, some of the input buffers are used and others are not. Since all the different input buffers electrically load their bond pad with capacitance whether they are used or not, their bond pad is loaded with more capacitance than a bond pad connected to a single input buffer, and, as a result, it takes longer for electronic signals to propagate through their bond pad than through the bond pad connected to the single input buffer.
An inventive device for reducing these anomalous differences in propagation time includes a plurality of programmable circuits, each including, for example, programmable elements such as fuses or anti-fuses. Each programmable circuit is coupled to an external communication terminal (e.g., a bond pad) of an IC die and to one of many load circuits (e.g, input buffers) in the die. The programmable circuits are configurable to load the terminal with one or more of the load circuits and to isolate the terminal from the rest of the load circuits. As a result, the programmable circuits can be configured to load the terminal with only those load circuits needed for a particular configuration of the die, and the total electrical load on the terminal is reduced. When the electrical load is capacitive, the reduced load on the terminal allows signals to propagate more quickly through the terminal and into or out of the die.
In another embodiment of the present invention, an IC die includes the inventive device described above along with the terminal and the load circuits described above. Still another embodiment includes the IC die described above with the programmable circuits configured to load the terminal with one or more of the load circuits and to isolate the terminal from the rest of the load circuits. In a further embodiment, a semiconductor wafer includes an integrated circuit having the terminal, load circuits, and programmable circuits described above. In an additional embodiment, an electronic system includes an input device, an output device, a memory device, and a processor device, and one of these devices includes the IC die described above.
In still another embodiment, an IC die includes a first load circuit communicating through a bond pad on the die with external circuitry in a first operating mode of the die. A second load circuit communicates through the bond pad with external circuitry in a second operating mode of the die. A first fuse interposed between the bond pad and the first load circuit couples the bond pad to the first load circuit in the first operating mode and programmably isolates the bond pad from the first load circuit in the second operating mode. Also, a second fuse interposed between the bond pad and the second load circuit couples the bond pad to the second load circuit in the second operating mode and programmably isolates the bond pad from the second load circuit in the first operating mode.
In a still further embodiment, a limiting apparatus limits the extent to which first and second load circuits in an IC die associated with first and second modes of the die electrically load a circuit node in the die. The apparatus includes first and second programmable circuits coupled to the circuit node and the first and second load circuits. The programmable circuits are configurable in the first mode to load the circuit node with the first load circuit and to isolate the circuit node from the second load circuit. Also, the programmable circuits are configurable in the second mode to load the circuit node with the second load circuit and to isolate the circuit node from the first load circuit.
In still another embodiment, an IC die includes the limiting apparatus, load circuits, and circuit node described above, and the programmable circuits are configured in the first mode to load the circuit node with the first load circuit and to isolate the circuit node from the second load circuit.
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IBM Technical Disclosure Bulletin, “Multiple Mode Selector for Input/Output Circuitry”, vol. 37, No. 7, Jul. 1994.
4 MEG DRAM Die, Micron Technology, Inc., Nov. 1996, pp. 1-4.
Cunningham Terry D.
Tra Quan
TraskBritt
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