Analog input selection circuit protected from negative...

Details Analog input selection circuit protected from negative... Analog input selection circuit protected from negative...

2002-08-01

2003-06-24

Vu, Bao Q. (Department: 2838)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000, C341S161000, C341S163000

Reexamination Certificate

active

06583748

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to analog input selection circuits that are protected from a negative over-voltage and supply analog voltage signals to a common analog-digital converter (“A/D converter”).
BACKGROUND OF THE INVENTION
An A/D converter formed on a semiconductor substrate typically has a plurality of analog input channels. Therefore, such A/D converters are provided with one analog input selection circuit for each analog input channel. The analog input selection circuits select one from among the plurality of analog input channels so that the selected analog input channel is connected to the A/D converter.
Assumed that there are two analog input selection circuits positioned adjacent to each other, the analog input channel corresponding to one of them has been connected to the A/D converter (“selected analog input selection circuit”) and the analog input channel corresponding to the other of them has not been connected to the A/D converter (“non-selected analog input selection circuit”). In this case, an over-voltage applied to an input terminal of the non-selected analog input selection circuit degrades the conversion accuracy in the A/D converter. As a countermeasure against this, for example, an over-voltage protection circuit is provided in each analog input selection circuit as shown in FIG.
3
. Over-voltage means both a positive over-voltage which exceeds a power supply voltage and a negative over-voltage which is lower than the ground voltage.
FIG. 3
is a circuit diagram which shows a configuration example of conventional analog input selection circuits. In
FIG. 3
, two analog input selection circuits
50
and
60
which are positioned adjacent to each other are commonly connected to an input terminal of an A/D converter
69
. The analog input selection circuits
50
and
60
are connected in parallel. Both the analog input selection circuits
50
and
60
have the same configuration.
In the analog input selection circuit
50
, serially connected transmission switches
52
and
53
, which are to be operated to conduct selection
on-selection, are provided between an input terminal
51
supplied with an analog voltage signal and a common A/D converter
69
. An over-voltage protection switch
54
is provided between a connection terminal of the switches
52
and
53
and the ground. A diode-connected PMOS transistor
56
is provided between the input terminal
51
and a power supply
55
. A diode-connected NMOS transistor
57
is provided between the input terminal
51
and the ground. The PMOS transistor
56
is a protection transistor for positive over-voltage, and the NMOS transistor
57
is a protection transistor for negative over-voltage.
In the analog input selection circuit
60
, serially connected transmission switches
62
and
63
, which are to be operated to conduct selection
on-selection, are provided between an input terminal
61
supplied with an analog voltage signal and the common A/D converter
69
. An over-voltage protection switch
64
is provided between a connection terminal of the switches
62
and
63
and the ground. A diode-connected PMOS transistor
66
is provided between the input terminal
61
and a power supply
65
. A diode-connected NMOS transistor
67
is provided between the input terminal
61
and the ground. The PMOS transistor
66
is a protection transistor for positive over-voltage, and the NMOS transistor
67
is a protection transistor for negative over-voltage.
Operation of the circuit shown in
FIG. 3
will now be explained.
FIG. 3
shows a state in which the analog input selection circuit
50
has been selected and is being used for A/D conversion and the analog input selection circuit
60
has not been selected. That is, in the analog input selection circuit
50
, the switch
54
is opened, and the switches
52
and
53
formed of transfer gates are closed. The input terminal
51
is thus connected to the A/D converter
69
, and the analog voltage signal applied to the input terminal
51
is transferred to the A/D converter
69
.
On the other hand, in the analog input selection circuit
60
, the switches
62
and
63
formed of transfer gates are opened. The connection between the input terminal
61
and the A/D converter
69
is thus disconnected. As a result, the analog voltage signal applied to the input terminal
61
is prevented from being transferred to the A/D converter
69
. The switch
64
is closed.
At this time, if a positive over-voltage which exceeds the power supply voltage is applied to the input terminal
51
of the analog input selection circuit
50
, the PMOS transistor
56
turns on to prevent the positive over-voltage from being input to the A/D converter
69
. If a negative over-voltage which is lower than the ground voltage is applied to the input terminal
51
, the NMOS transistor
57
turns on to prevent the negative over-voltage from being input to the A/D converter
69
.
On the other hand, if a positive over-voltage which exceeds the power supply voltage is applied to the input terminal
61
of the analog input selection circuit
60
, the PMOS transistor
66
turns on to prevent an undesired current from flowing in the analog input selection circuit
60
. If a negative over-voltage which is lower than the ground voltage is applied to the input terminal
61
, the NMOS transistor
67
turns on to prevent an undesired current from flowing in the analog input selection circuit
60
.
As a matter of fact, even if the switches
62
and
63
are open in the non-selected analog input selection circuit
60
, however, an undesired current caused by an over-voltage is sometimes transferred to the A/D converter
69
through the switches
62
and
63
, resulting in a lowered conversion accuracy of the A/D converter
69
.
Therefore, the switches
54
and
64
for over-voltage protection are provided. In the non-selected analog input selection circuit
60
, which is not being used for A/D conversion, the switch
64
is closed to draw the undesired current which flows through the switches
62
and
63
to the ground and thereby ensure the accuracy of the A/D converter
69
. In the analog input selection circuit
50
as well, the switch
54
is closed when the analog input selection circuit
50
is not selected.
However, the conventional analog input selection circuit has a problem that the influence of over-voltage cannot be sufficiently excluded although the over-voltage protection circuit is provided. Hereafter, the problem will be explained by referring to
FIGS. 4 and 5
.
FIG. 4
is a sectional view which shows an N-well CMOS process of PMOS transistors shown in FIG.
3
.
FIG. 5
is a sectional view which shows an N-well CMOS process of NMOS transistors shown in FIG.
3
.
With reference to
FIG. 4
, in a main surface of a P-type substrate
70
, two N-well regions
71
and
72
are formed on both sides of a formation region of an oxide film
73
. A PMOS transistor is formed in each of the two N-well regions
71
and
72
.
A P+ channel
74
and a P+ channel
75
are formed in a first N-well region
71
. A source electrode, which is not shown, is formed in the P+ channel
74
. A drain electrode, which is not shown, is provided in the P+ channel
75
. A gate electrode
76
is provided on the surface between the P+ channel
74
and the P+ channel
75
. A first one of the PMOS transistors shown in
FIG. 3
is formed of them. The source electrode, which is provided in the P+ channel
74
and which is not shown, is connected to a power supply
77
. The drain electrode, which is provided in the P+ channel
75
and which is not shown, is connected to an input terminal
78
supplied with an analog voltage signal.
A P+ channel
79
and a P+ channel
80
are formed in a second N-well region
72
. A source electrode, which is not shown, is provided in the P+ channel
79
. A drain electrode, which is not shown, is provided in the P+ channel
80
. A gate electrode
81
is provided on the surface between the P+ channel
79
a

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