Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-08-30
2003-06-10
Paladini, Albert W. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S127000, C438S124000, C438S126000
Reexamination Certificate
active
06576495
ABSTRACT:
TECHNICAL FIELD
The present invention relates to microelectronic substrate packages having a pre-disposed fill material for mounting the package to a supporting member.
BACKGROUND
Packaged microelectronic assemblies, such as memory chips and microprocessor chips, typically include a microelectronic substrate die encased in a plastic, ceramic or metal protective covering. The die includes functional devices or features, such as memory cells, processor circuits and interconnecting wiring. The die also typically includes bond pads electrically coupled to the functional devices. The bond pads can be coupled to pins or other types of terminals that extend outside the protective covering for connecting to buses, circuits, and/or other microelectronic assemblies.
One conventional “flip chip” package
10
shown in plan view in
FIG. 1
includes a microelectronic die
20
having a downwardly facing surface
24
with solder ball pads
22
, and an upwardly facing surface
23
opposite the downwardly facing surface
24
. Solder balls
21
are attached to the solder ball pads
22
and dipped in flux. The die
20
is then positioned with the downwardly facing surface
24
facing toward a printed circuit board (PCB)
30
to engage the solder balls
21
with corresponding bond pads
31
on the PCB
30
. The solder balls
21
are partially melted or “reflowed” and solidified to form structural and electrical bonds with the bond pads
31
on the PCB
30
.
In one aspect of the arrangement shown in
FIG. 1
, a gap corresponding roughly to the diameter of the solder balls
21
remains between the upper surface of the PCB
30
and the downwardly facing surface
24
of the die
20
after the die
20
has been attached. The gap can be detrimental to the integrity and performance of the die
20
because it can allow oxidizing agents and other contaminants to attack the solder ball bond between the die
20
and the PCB
30
. Furthermore, the gap can reduce the rate at which heat is transferred away from the die
20
, reducing the life expectancy and/or the performance level of the die
20
.
To alleviate the foregoing drawbacks, an underfill material
40
is typically introduced into the gap between the die
20
and the PCB
30
. For example, in one conventional approach, a bead of flowable epoxy underfill material
40
is positioned on the PCB
30
along two edges of the die
20
. The underfill material
40
is heated until it flows and fills the gap by capillary action, as indicated by arrows “A”. The underfill material
40
can accordingly protect the solder ball connections from oxides and other contaminants, and can increase the rate at which heat is transferred away from the die
20
. The underfill material
40
can also increase the rigidity of the connection between the die
20
and the PCB
30
to keep the package
10
intact during environmental temperature changes, despite the fact that the die
20
, the solder balls
21
and the PCB
30
generally have different coefficients of thermal expansion.
One drawback with the capillary action approach described above for applying the underfill material
40
is that the underfill material
40
can take up to
20
minutes or longer to wick its way to into the gap between the die
20
and the PCB
30
. Accordingly, the capillary underfill process can significantly increase the length of time required to produce the packages
10
. One approach to addressing this drawback (typically referred to as a “no-flow” process) is to first place the underfill material directly on the PCB
30
and then place the die
20
on the underfill material. For example, as shown in
FIG. 2A
, a quantity of underfill material
40
a
having an integrated quantity of flux can be disposed on the PCB
30
adjacent to the bond pads
31
. As shown in
FIG. 2B
, the die
20
can be lowered onto the PCB
30
until the solder balls
21
contact the bond pads
31
of the PCB
30
. As the solder balls
21
approach the bond pads
31
, the die
20
contacts the underfill material
40
a
and squeezes the underfill material
40
a
outwardly around the solder balls
21
and between the downwardly facing surface
24
of the die
20
and the upper surface of the PCB
30
, as indicated by arrows “B”. An encapsulating material
70
is then disposed on the die
20
and the PCB
30
.
One problem with the no-flow process described above with reference to
FIGS. 2A-2B
is that air bubbles can become trapped between the die
20
and the PCB
30
. The air bubbles can reduce the effective bond area between the die
20
and the PCB
30
and can make the die
20
more likely to separate from the PCB
30
. Furthermore, oxygen in the air bubbles can oxidize the connection between the solder balls
21
and the solder ball pads
22
and/or the bond pads
31
to reduce the integrity of the structural and/or electrical connections between the die
20
and the PCB
30
.
Another problem with the process described above with reference to
FIGS. 2A-2B
is that it can be difficult to accurately meter the amount of underfill material
40
a
applied to the PCB
30
. For example, if too little underfill material
40
a
is provided on the PCB
30
, the solder balls
21
may not be adequately covered. Even if the underfill material
40
a
extends beyond the solder balls
21
to the edge of the die
20
(as indicated in dashed lines in
FIG. 2B
by position P
1
), it can exert a tensile force on the die
20
that tends to separate the die
20
from the PCB
30
. Conversely, if too much underfill material
40
a
is provided on the PCB
30
, the underfill material can extend over the upperwardly facing surface
23
of the die
20
(as indicated in dashed lines in
FIG. 2B
by position P
2
), and can form protrusions
49
. The protrusions
49
can be subjected to high stress levels when the die
20
is encapsulated with the encapsulating material
70
, and can cause the underfill material
40
a
to separate from the die
20
. Still further, the underfill material
40
a
can become trapped between the solder balls
21
and the bond pads
31
and can interfere with the electrical connections between the die
20
and the PCB
30
.
SUMMARY
The present invention is directed toward microelectronic device packages and methods for forming such packages by bonding microelectronic substrates to support members, such as PCBs. A method in accordance with one aspect of the invention includes disposing a fill material in a fill region defined by a surface of the microelectronic substrate before engaging the fill material with the support member. The fill region can also be defined in part by a bond member (such as a solder ball) or other protrusion projecting away from the surface of the microelectronic substrate. The method can further include engaging the fill material with the support member after disposing the fill material in the fill region, and connecting the bond member and the fill material to the support member. The microelectronic substrate and the fill material can then be at least partially enclosed with an encapsulating material.
In one aspect of the invention, the microelectronic substrate is dipped into a vessel of fill material and is then removed from the vessel with a portion of the fill material attached to the surface of the microelectronic substrate. Accordingly, the fill material can have a thixotropic index with a value of from about four to about six. In another aspect of the invention, the surface of the microelectronic substrate can be a first surface and the microelectronic substrate can include a plurality of second surfaces extending away from the first surface, and a third surface facing opposite the first surface. The extent to which the fill material engages the second surfaces of the microelectronic substrate can be controlled so that the fill material engages a portion of the second surfaces extending from the first surface to a point about 60% to about 70% of the distance from the first surface to the third surface of the microelectronic substrate.
The invention is also directed toward a microelectro
Fuller Jason L.
Jiang Tongbi
Wood Alan G.
Micro)n Technology, Inc.
Paladini Albert W.
Perkins Coie LLP
Zarneke David A.
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