Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Housing or package filled with solid or liquid electrically...
Reexamination Certificate
2002-05-15
2003-12-09
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Housing or package filled with solid or liquid electrically...
C257S774000, C257S777000
Reexamination Certificate
active
06661086
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a configuration for electrically connecting semiconductor chips arranged one above the other in a three-dimensionally embodied circuit. The circuit includes interconnects, which are led from one active surface of a semiconductor chip through the semiconductor chip to the other surface, opposite the first active surface of the semiconductor chip. Contact plugs, via which the semiconductor chips are arranged one above the other are electrically connected to one another.
In electronic devices, such as, for example, personal computers (PC), laptops, electronic notebooks, etc., the packing density is intended to be as high as possible through three-dimensional or 3D arrangement of semiconductor chips used in the devices. One example of such a 3D arrangement is the microprocessor semiconductor chip sold under the trademark PENTIUM™, which is provided directly on a 1 gigabit DRAM memory semiconductor chip and which is accommodated together with the DRAM memory semiconductor chip in a common housing.
Previously, the electrical connection between such semiconductor chips has preferably been established by bonding using wires or electrically conductive connections on circuit boards. Both require additional space for routing the bonding wires or for accommodating the circuit boards, so that limits are imposed on an increase in the packing density.
U.S. Pat. No. 5,608,264 describes a surface-mounted integrated circuit in which oxide layers are provided between interconnects and semiconductor chips.
Furthermore, U.S. Pat. No. 5,528,080 discloses a circuit arrangement in which interconnects are produced by a thermomigration of conductive material in a semiconductor body in order to produce electrical connections between mutually opposite surfaces. Similar conductive connections which are produced by thermomigration and form pn junctions are also described in U.S. Pat. No. 3,904,442.
Finally, interconnects produced by thermomigration between different surfaces of a semiconductor body are also disclosed in U.S. Pat. No. 4,761,681 and U.S. Pat. No. 4,612,083.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a three-dimensionally embodied circuit which overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, it is an object of the invention to provide a configuration for electrically connecting semiconductor chips in a three-dimensionally embodied circuit which allows a particularly high packing density to be achieved for the semiconductor chips and which can nevertheless ensure a reliable insulation of interconnects from other zones of the semiconductor chip.
With the foregoing and other objects in view there is provided, in accordance with the invention, a three-dimensionally embodied circuit, that includes a plurality of semiconductor chips configured one above another. The plurality of the semiconductor chips include a first semiconductor chip. The first semiconductor chip has an active first surface, a second surface opposite the active first surface, interconnects running from the active first surface to the second surface, and other zones. Contact plugs electrically connect the plurality of the semiconductor chips together. The first semiconductor chip includes regions surrounding the interconnects. The regions cooperate with the interconnects such that each one of the interconnects is electrically insulated from the other zones of the first semiconductor chip by a pn junction. The regions are formed by a thermomigration of a conductive material.
In accordance with an added feature of the invention, the first semiconductor chip has an n-conducting semiconductor body; and the conductive material is aluminum.
In accordance with an additional feature of the invention, the first semiconductor chip has a p-conducting semiconductor body; and the conductive material is arsenic.
In accordance with another feature of the invention, the contact plugs are provided on the active first surface of the first semiconductor chip.
In accordance with a further feature of the invention, the contact plugs are formed from aluminum.
In accordance with a further added feature of the invention, the first semiconductor chip is composed of silicon.
The object of the invention is achieved by virtue of the fact that the interconnects are surrounded by regions produced by thermomigration of a conductive material and are thereby electrically insulated from other zones of the semiconductor chip by a pn junction.
For the electrical connection of semiconductor chips in a 3D arrangement, it is inherently possible to utilize thermomigration instead of the widened bonding wires or circuit boards. By way of example, aluminum is applied to an n-conducting silicon wafer by vapor deposition and is patterned. A temperature gradient is then produced in the silicon wafer by using a rapid thermal treatment (RTP). The aluminum applied to the silicon wafer then starts to migrate along the temperature gradient in the silicon wafer and forms a highly doped p-conducting region there. Such a region requires a time duration of a few minutes to pass through the silicon wafer, depending on the layer thickness of the silicon wafer.
By utilizing this thermomigration, for example, of aluminum in an n-conducting silicon wafer, it is thus possible to produce vertical conductive interconnects or channels from the active surface of a semiconductor chip embodied in the semiconductor wafer as far as the rear side of the chip.
If n-conducting channels are intended to be produced in a p-conducting silicon wafer, then thermomigration of arsenic may be performed.
Instead of the conductive materials specified namely aluminum and arsenic, it is also possible, if appropriate, to use other substances.
The channels forming interconnects are always produced below pads or contact pads, to be produced later, from one active surface of the semiconductor wafer. These channels or interconnects therefore require no additional area.
In the inventive configuration, then, interconnects are surrounded by regions produced by thermomigration of a conductive material, in order to ensure electrical insulation from other zones of the semiconductor chip by means of the pn junction thereby formed.
A second semiconductor chip that is to be connected to a semiconductor chip acquires plugs on its active surface. These plugs may be composed of aluminum, for example, and the surface of these plugs is provided in a pattern that corresponds to the pattern of the channels on the opposite top side of the first-mentioned semiconductor chip. This second semiconductor chip then has placed on it the first semiconductor chip with its opposite surface, so that the channels which end there make contact with the aluminum plugs.
After the thermomigration, the individual surfaces of the semiconductor wafers forming the semiconductor chips may be subjected to aftertreatment in a customary manner by chemical mechanical polishing or chemical reactions, in order thus to prepare the surfaces for the next steps.
Other features which are considered as characteristic for the invention are set forth in the appended claims. Although the invention is illustrated and described herein as embodied in a configuration for electrically connecting chips in a three-dimensionally embodied circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
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Andújar Leonardo
Flynn Nathan J.
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