Semiconductor device

Details Semiconductor device Semiconductor device

2000-12-01

2003-08-26

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C257S211000

Reexamination Certificate

active

06611010

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-345298, filed Dec. 3, 1999; and No. 2000-006706, filed Jan. 14, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
(1) Background 1
The present invention relates to contact structures in semiconductor devices such as a semiconductor memory and the like, and more particularly to contact structures in a non-volatile semiconductor memory (for example, a bit line contact structure, a source line contact structure and the like).
As an example of conventional non-volatile semiconductor memories, a NAND cell type flash memory will be described below in terms of its device structure.
A NAND cell type flash memory has a memory cell array comprised of a plurality of NAND cell units. Each of the NAND cell units is comprised of a plurality of memory cells connected in series and a pair of select transistors, each connected to both ends of the NAND cell unit. The select transistors are connected between a bit line and a source line.
Each of the memory cells comprises an n-channel MOS transistor having a so-called stacked gate structure in which a control gate electrode is stacked on a floating gate electrode. Each of the select transistors comprises an n-channel MOS transistor having a structure similar to the memory cell, i.e., a structure in which an upper electrode is stacked on a lower electrode. However, it is, for example, the lower electrode which actually functions as a gate electrode of the select transistor.
In two adjacent transistors of the plurality of transistors within a NAND cell unit (memory cells, select transistors), one source region or one drain region is shared by these two transistors.
In the following, a specific structure of the NAND cell type flash memory will be described.
FIG. 1
is a circuit diagram illustrating a portion of a memory cell array in the NAND cell type flash memory.
A NAND cell unit is comprised of a plurality (four, eight, 16 or the like) of memory cells connected in series, and a pair of select transistors, each connected to one of both ends of the NAND cell unit. Also, the NAND cell units are connected between bit lines BL
0
, . . . , BL
63
and source lines SL. The source lines SL are connected to reference potential lines (wirings for shunting) formed of a conductive material such as aluminum, polysilicon or the like, at predetermined locations.
The source lines SL extend in a row direction, while the bit lines BL
0
, . . . , BL
63
and the reference potential lines extend in a column direction. Contact sections of the source lines SL with the reference potential lines are provided, for example, each time the source lines SL intersect 64 bit lines BL
0
, . . . , BL
63
. The reference potential lines are connected to a so-called peripheral circuit arranged around the memory cell array.
Word lines (control gate lines) WL
1
, . . . , WLn extend in the row direction, and select gate lines SG
1
, SG
2
also extend in the row direction. A set of memory cells connected to a single word line (control gate line) WLi is called a page. Also, a set of memory cells connected to the word lines WL
1
, . . . , WLn sandwiched between the two select gate lines SG
1
, SG
2
is called a NAND block or simply a block.
One page is comprised, for example, of 256 bytes (256×8) of memory cells. The memory cells within one page are written substantially at the same time. Also, when one page is comprised of 256 bytes of memory cells with one NAND cell unit comprised of eight memory cells, one block is comprised of 2,048 bytes (2048×8) of memory cells. The memory cells within one block are erased substantially at the same time.
FIG. 2
is a top plan view illustrating the device structure of one NAND cell unit within the memory cell array.
FIG. 3
is a cross-sectional view taken along the line III—III in
FIG. 2
, and
FIG. 4
is a cross-sectional view taken along the line IV—IV in FIG.
2
.
FIG. 5
in turn illustrates an equivalent circuit of the device of
FIGS. 2 through 4
.
A p-type substrate (p-sub)
11
-
1
is formed therein a so-called double well region which comprises an n-type well region (Cell n-well)
11
-
2
and a p-type well region (Cell p-well)
11
-
3
. Memory cells and select transistors are formed in the p-type well region
11
-
3
.
Memory cells and select transistors are arranged within an element area within the p-type well region
11
-
3
. The element area is surrounded by an element isolation oxide film (element isolation area)
12
formed on the p-type well region
11
-
3
.
In this example, as illustrated in
FIG. 5
, one NAND cell unit is comprised of eight memory cells M
1
-M
8
connected in series, and a pair of select transistors S
1
, S
2
, each of which is connected to one of both ends of the NAND cell unit.
Each of the memory cells is comprised of a silicon oxide film (gate insulating film)
13
formed on the p-type well region (Cell p-well)
11
-
3
; a floating gate electrode
141
,
142
, . . . ,
148
on the silicon oxide film
13
; a silicon oxide film (interpoly insulating film)
15
on the floating gate electrodes
141
,
142
, . . . ,
148
; a control gate electrode
161
,
162
, . . . ,
168
on the silicon oxide film
15
; and source/drain regions
19
within the p-well region (Cell p-well)
11
-
3
.
Each of the select transistors in turn is comprised of the silicon oxide film (gate insulating film)
13
formed on the p-type well region
11
-
3
; gate electrodes
14
9
,
14
10
or
16
9
,
16
10
on the silicon oxide film
13
; and source/drain regions
19
,
19
(S),
19
(D) within the p-well region
11
-
3
.
The structure of the select transistors is similar to the structure of the memory cells, as appreciated from the foregoing. This is because the memory cells and the select transistors are simultaneously formed in the same process to reduce the number of steps involved in the process and accordingly reduce the manufacturing cost.
The memory cell differs from the select transistors in structure in the following aspects.
As illustrated in
FIG. 6
, in regard to the memory cells, a floating gate electrode
14
1
, . . . ,
14
8
is provided for each of memory cells, the control gate electrodes
16
1
, . . . ,
16
8
extend on the memory cell array linearly in the row direction, and contact sections W for the control gate electrodes
16
1
, . . . ,
16
8
are provided at ends of the control gate electrodes
16
1
, . . . ,
16
8
in the row direction.
On the other hand, in regard to the select transistors, the gate electrodes
14
9
,
14
10
as lower electrodes, for example, are provided in common to a plurality of select transistors in the row direction, and contact sections SS, SD for the gate electrodes
149
,
1410
are provided at regular intervals on the memory cell array.
Turning back to description on
FIGS. 2 through 5
, one set of source/drain regions (n
+
-type diffusion layers)
19
is shared by two adjacent transistors of a plurality of transistors (memory cells, select transistors) within the NAND cell unit.
The memory cells and the select transistors are overlain by a silicon oxide film (CVD oxide film)
17
formed by a CVD (chemical vapor deposition) method. A bit line
18
is routed on the CVD oxide film
17
. The bit line
18
is connected to one end of the NAND cell unit, i.e., the n
+
-type diffusion layer
19
(D) through a contact plug
20
.
In a non-volatile semiconductor memory including the NAND cell-type flash memory as descried above, researches and developments for miniaturization and higher integration of memory cells are under progress in order to increase the memory capacity (the number of bits) in one chip.
However, to achieve the miniaturization and higher integration of memory cells, problems associated therewith must be solved to achieve an improved reliability. The problems involved in the miniaturization and higher integration include an increase in wiring resistance and c

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