Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Reexamination Certificate
2001-06-18
2003-12-30
Valentine, Donald R. (Department: 1742)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S143000, C205S148000, C205S252000, C205S253000
Reexamination Certificate
active
06669834
ABSTRACT:
BACKGROUND OF THE INVENTION
Soldering has been a familiar technique for forming electrical and/or mechanical connections between metal surfaces and is the technique of choice for many applications in the electronics industry. Many soldering techniques have therefore been developed for applying solder to surfaces or interfaces between metals to extend soldering techniques to many diverse applications.
In the electronics industry, in particular, the trend toward smaller sizes of components and higher integration densities of integrated circuits has necessitated techniques for application of solder to extremely small areas and in carefully controlled volumes to avoid solder bridging between conductors.
High performance microelectronic devices often use solder balls or solder bumps for electrical interconnection to other microelectronic devices. For example, a very large scale integration (VLSI) chip may be electrically connected to a circuit board or other next level packaging substrate using solder balls or solder bumps. This connection technology is also referred to as “Controlled Collapse Chip Connections—C4” or “flip-chip” technology, and is often referred to as solder bumps.
In accordance with one type of solder bump technology developed by IBM, the solder bumps are formed by evaporation through openings in a shadow mask which is clamped to an integrated circuit wafer. For example, U.S. Pat. No. 5,234,149 entitled “Debondable Metallic Bonding Method” to Katz et al. discloses an electronic device with chip wiring terminals and metallization layers. The wiring terminals are typically primarily aluminum, and the metallization layers may include a titanium or chromium localized adhesive layer, a co-deposited localized chromium copper layer, a localized wettable copper layer, and a localized gold or tin capping layer. An evaporated localized lead-tin solder layer is located on the capping layer.
Solder bump technology based on an electroplating method has also been actively pursued. In this method, an “under bump metallurgy” (UBM) layer is deposited on a microelectronic substrate having contact pads thereon, typically by evaporation or sputtering. A continuous under bump metallurgy layer is typically provided on the pads and on the substrate between the pads, in order to allow current flow during solder plating.
An example of an electroplating method with an under bump metallurgy layer is disclosed in U.S. Pat. No. 5,162,257 entitled “Solder Bump Fabrication Method” to Yung. In this patent, the under bump metallurgy layer contains a chromium layer adjacent the substrate and pads, a top copper layer which acts as a solderable metal, and a phased chromium/copper layer between the chromium and copper layers. The base of the solder bump is preserved by converting the under bump metallurgy layer between the solder bump and contact pad into an intermetallic of the solder and the solderable component of the under bump metallurgy layer. Multiple etch cycles may, however, be needed to remove the phased chromium/copper layer and the bottom chromium layer. Even with multiple etch cycles, the under bump metallurgy layer may be difficult to remove completely, creating the risk of electrical shorts between solder bumps. U.S. Pat. No. 5,767,010, titled “Solder Bump Fabrication Methods and Structure Including a Titanium Barrier Layer”, issued Jun. 16, 1998, purports to address this problem.
Several technical problems are typically associated with electroplating of tin/lead solder on semiconductor wafers and other microelectronic workpieces. One problem relates to the relatively low rate at which deposition of the solder takes place. Generally, the upper deposition rate for selectively depositing solder on the surface of a microelectronic workpiece is about 1 micron/minute. Attempts to significantly increase the deposition rate have heretofore proven unsuccessful. Most such attempts are hindered by the fact that a significant amount of gas evolves during the electroplating process, particularly when traditional inert anodes are employed. The resulting gas bubbles impair the proper formation of the solder bumps and other structures formed from the solder deposit. Additionally, removal of the evolved gases can be problematic. The microelectronic fabrication industry thus has been forced to accept low deposition rate solder processes and equipment.
Several technical problems must be overcome in designing reactors used in the electroplating of semiconductor wafers. Utilization of a small number of discrete electrical contacts (e.g., 6 contacts) with the seed layer about the perimeter of the wafer ordinarily produces higher current densities near the contact points than at other portions of the wafer. This non-uniform distribution of current across the wafer, in turn, causes non-uniform deposition of the plated solder material. Current thieving, effected by the provision of electrically-conductive elements other than those which contact the seed layer, can be employed near the wafer contacts to minimize such non-uniformity. But such thieving techniques add to the complexity of electroplating equipment, and increase maintenance requirements.
Another problem with electroplating of wafers concerns efforts to prevent the electric contacts themselves from being plated during the electroplating process. Any solder plated to the electrical contacts must be removed to prevent changing contact performance. While it is possible to provide sealing mechanisms for discrete electrical contacts, such arrangements typically cover a significant area of the wafer surface, and can add complexity to the electrical contact design.
In addressing a further problem, it is sometimes desirable to prevent electroplating on the exposed barrier layer near the edge of the semiconductor wafer. Electroplated solder may not adhere well to the exposed barrier layer material, and is therefore prone to peeling off in subsequent wafer processing steps. Further, solder that is electroplated onto the barrier layer within the reactor may flake off during the electroplating process thereby adding particulate contaminants to the electroplating bath. Such contaminants can adversely affect the overall electroplating process.
The specific solder to be electroplated can also complicate the electroplating process. For example, electroplating of solder may require use of a seed layer having a relatively high electrical resistance. As a consequence, use of the typical plurality of electrical wafer contacts (for example, six, (6) discrete contacts) may not provide adequate uniformity of the plated metal layer on the wafer.
Beyond the contact related problems discussed above, there are also other problems associated with electroplating reactors for solder plating. As device sizes decrease, the need for tighter control over the processing environment increases. This includes control over the contaminants that affect the electroplating process. The moving components of the reactor, which tend to generate such contaminants, should therefore be subject to strict isolation requirements.
Still further, existing electroplating reactors are often difficult to maintain and/or reconfigure for different electroplating processes. Such difficulties must be overcome if an electroplating reactor design is to be accepted for large-scale manufacturing.
SUMMARY OF THE INVENTIONS
The present invention is accordingly directed to an improved electroplating method, chemistry, and apparatus for selectively depositing tin/lead solder bumps and other structures at a high deposition rate pursuant to manufacturing a microelectronic device from a workpiece, such as a semiconductor wafer. An apparatus for plating solder on a microelectronic workpiece in accordance with one aspect of the present invention comprises a reactor chamber containing an electroplating solution having free ions of tin and lead for plating onto the workpiece. A chemical delivery system is used to deliver the electroplating solution to the reactor chamber at a high flow rate. A workpiece support is used th
Batz, Jr. Robert W.
Conrady Scot
Ritzdorf Thomas L.
Christensen O'Connor Johnson & Kindness PLLC
Semitool Inc.
Valentine Donald R.
LandOfFree
Method for high deposition rate solder electroplating on a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for high deposition rate solder electroplating on a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for high deposition rate solder electroplating on a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3118629