Method to reduce skew in clock signal distribution using...

Details Method to reduce skew in clock signal distribution using... Method to reduce skew in clock signal distribution using...

2000-02-18

2003-11-25

Frejd, Russell (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S013000, C703S019000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06654712

ABSTRACT:

TECHNICAL FIELD
The invention relates to the design of digital electronic circuitry. More particularly, the invention relates to a method for reducing the skew in clock signal distribution by balancing wire widths in an electronic circuit.
BACKGROUND ART
In the design of electronic circuits, particularly microprocessors, it is important to produce a circuit which has a clock signal that arrives simultaneously on all latches within the circuit. This simultaneous clock signal arrival is a key factor in obtaining proper functioning of the circuit. Distributing a clock signal simultaneously throughout a microchip is a difficult challenge because it involves a number of factors, including distance along the paths of the circuit, resistance and capacitance delays, different loads at the ends of the paths, and other complicating factors. It has been necessary to develop special techniques to balance the distribution paths for the clock signal so that it arrives at the end of all of the paths at the same time.
There are techniques for balancing the metal in a circuit if there is total symmetry in the circuit paths, but in practical cases the end points for the clock signal are not symmetrically placed throughout the chip. The general solution used in the art has been to modify the widths of the wires in circuit trees such that the resulting changes in resistance and capacitance along those wires balances the distribution times for the clock signal to all end points. For this type of solution there exists a simplified formula called the Elmore delay model which will determine the delay from a source, to the sink at the end point, i.e., a leaf, in a circuit tree. (see
Optimal Wiresizing Under Elmore Delay Model
, Cong, J. J. and Leung, K-S,
IEEE Trans. on CAD of Integrated Circuits
, Vol. 14, No. 3, March, 1995, 321-335.) The Elmore delay model adds all of the down stream capacitance from a given node, multiplies that by the resistance of the piece of wire that leads to the given node, and then adds that value into a total delay from the given node to each individual leaf. So, the delay from the source to the leaf is calculated by adding together the delay along each segment along the way. The delay along each segment is calculated by multiplying the resistance of that segment with the capacitance down stream from it. The Elmore formula has been the basis for clock signal delay optimization software up to this point. The Elmore model is, however, somewhat inaccurate since it does not model all the effects on a signal in a circuit.
There do exist certain improvements on the Elmore model and some current CAD tools use such improved methods to calculate optimized wire widths. The problems associated with those methods, however, is that there exists another effect that is becoming more important as circuits are reach feature sizes as small as those now being developed in microchip design. That effect is inductance, and there is currently no way to include inductance in the Elmore delay model.
Instead, there are circuit simulations which model all of the resistance, capacitance, and inductance components, such as the SPICE circuit simulation, which is well known in the art. (see Kielkowski, Ron M., 1994
, Inside Spice
, New York, McGraw Hill; and Sandler, Steven M.,
SMPS simulation with SPICE
, 1996, McGraw Hill) SPICE is a circuit level simulator and is basically the microchip design industry's standard method for assessing how a circuit is going to operate in reality.
There is a need for improved methods and apparatus for reducing skew in clock signal distribution in an electronic circuit.
SUMMARY OF INVENTION
The improved methods and apparatus incorporate the accuracy of such circuit simulations into a method for improving the balancing of wire widths to reduce the skew in clock signal distribution. Instead of just attempting to predict the delays on a circuit with a model such as Elmore, one can run simulations that send signals through simulated wires and then note what the arrival times for the signal are at the leaves. Adjustments can then be made to the wire widths based upon any disparities that are found. Instead of using Elmore models to set the wires width, the improved methods and apparatus use the wire widths that exist at the current stage of a design to form a stimulation, and uses the Elmore model as a predictor of what changes that should be made to the wire widths to achieve the delays derived in the simulation.
In one respect, what is described is a method to reduce variations in signal delays along paths in a design of an integrated circuit by balancing wire widths. The method comprises performing a circuit simulation to determine simulated signal delays along the circuit paths based on first wire widths for a given circuit, then running a delay model analysis to calculate predicted signal delays along the circuit paths based on first wire widths for the given circuit. The method then calculates a correction difference between the predicted signal delays and the simulated signal delays, and derives delay targets from the correction difference. Finally, the method calculates second wire widths using the delay model analysis to meet the delay targets. Preferably, the signal delays are clock signal delays, the circuit simulation is a SPICE circuit simulation, and the delay model is an Elmore delay model.
In another respect, what is described is a system for reducing variations in clock signal delays. The system comprises a Central Processing Unit (CPU), memory containing an instruction set for wire width balancing operably connected to the CPU, memory containing a circuit simulation instruction set operably connected to the CPU, memory containing a delay model instruction set operably connected to the CPU, and means for outputting or displaying wire width information. The system operates such that the CPU uses the wire width balance, the circuit simulation, and the delay model instruction sets to determine wire width information.
In yet another respect, what is described is a computer readable medium on which is embedded a program. The embedded program comprises components that execute the above method.


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