Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-03-13
2003-10-28
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185220, C365S185290, C365S185330
Reexamination Certificate
active
06639844
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to flash memory devices and in particular to flash memory devices having multi-bit flash memory cells. Even more particularly, this invention relates to a method of programming, erasing, verifying erasure and overerase correction of the bits.
2. Discussion of the Related Art
Flash memory is a type of electronic memory media that can be rewritten which can hold its contents without the consumption of power. Flash memory devices are designed to have life spans from 100K to 300K write cycles. Unlike dynamic random access memory (DRAM) devices and static random memory (SRAM) devices in which a single byte can be erased, flash memory devices are typically erased and written in fixed multi-bit blocks or sectors. Flash memory technology evolved from electrically erasable read only memory (EEPROM) chip technology, which can be erased in place. Flash memory devices are less expensive and denser. This new category of EEPROMs has emerged as an important non-volatile memory that combines the advantages of erasable programmable read only memory (EPROM) density with EEPREOM electrical erasability.
Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each cell. In such single bit memory architectures, each cell typically includes a metal oxide semiconductor (MOS) transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
The control gate is connected to a wordline associated with a row of such cells to form sectors of such cells in a typical NOR configuration. In addition, the drain regions of the cells are connected together by a conductive bitline. The channel of the cell conducts current between the source and the drain in accordance with an electric field developed in the channel by the stacked gate structure. In the NOR configuration, each drain terminal of transistors within a single column is connected to the same bitline. In addition, each flash cell has its stacked gate terminal connected to a different wordline, while all the flash cells in the array have their source terminals connected to a common source terminal. In operation, individual flash cells are addressed via the respective bitline and wordline using peripheral decoder and control circuitry for programming (writing), reading or erasing function.
Such a single bit stacked gate flash memory cell is programmed by applying a voltage to the control gate and connecting the source to ground and the drain to a predetermined potential above the source. A resulting high electric field across the tunnel oxide leads to a phenomenon called “Fowler-Nordheim” tunneling. During this process, electrons in the core cell channel region tunnel through the gate oxide into the floating gate and become trapped in the floating gate since the floating gate is surrounded by the interpoly dielectric and the tunnel oxide. As a result of the trapped electrons, the threshold voltage of the cell increases. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons causes the cell to be programmed.
In order to erase a typical single bit stacked gate flash memory cell, a voltage is applied to the source and the control gate is held at a negative potential, while the drain is allowed to float. Under these conditions, an electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the source region. The electrons are then extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. As the electrons are removed from the floating gate, the cell is erased.
In conventional single bit flash memory devices, erase verification is performed to determine whether each cell in a block or set of such cells has been properly erased. Current single bit erase verification methodologies provide for verification of bit or cell erasure, and application of supplemental erase pulses to individual cells that fail the initial verification. Thereafter, the erased status of the cell is again verified and the process continues until the cell or bit is successfully erased or the cell is marked as unusable.
Recently, dual bit flash memory cells have been introduced that allow the storage of two bits of information in a single memory cell. The conventional programming and erase verification methods employed with single bit stacked gate architectures are not adequate for such dual bit devices. The dual bit flash memory structures that have been introduced do not utilize a floating gate, such as an ONO flash memory device that employs a polysilicon layer over the ONO layer for providing wordline connections. Conventional techniques do not address the characteristics associated with these types of devices. Therefore, there is an unmet need in the art for new and improved programming methods, improved erase verification methods, improved overerase correction methods and systems that ensure proper programming and erasure of data bits in a dual bit memory architecture and which account for the structural characteristics thereof.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are obtained by a method of erasing and soft programming of the normal and complementary bits of the dual bit memory device.
In accordance with an aspect of the invention, a soft programming pulse having a ratio of V
g
/V
d
≧2 is applied to overerased bits if the maximum soft programming pulse has not been reached.
The described method thus provides a method of overerase correction for a multi-bit flash memory device.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 5930174 (1999-07-01), Chen et al.
patent: 6172909 (2001-01-01), Haddad et al.
patent: 6331951 (2001-12-01), Bautista, Jr. et al.
patent: 6456533 (2002-09-01), Hamilton et al.
patent: 6493266 (2002-12-01), Yachareni et al.
He Yi
Liu Zhizheng
Randolph Mark W.
Advanced Micro Devices , Inc.
Nelms David
Yoha Connie C.
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