Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-01-24
2003-06-10
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185200, C365S200000, C365S210130, C365S230060
Reexamination Certificate
active
06577534
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and in particular, to a non-volatile semiconductor memory device which has a high access rate to a non-defective sector.
2. Description of the Related Art
Referring to
FIG. 7
, a conventional non-volatile semiconductor memory device
300
includes a redundant circuit
310
, a row decoder
320
, a word line driver
330
, a memory cell array
340
, and a read/write circuit
350
.
The memory cell array
340
is composed of a redundant area
341
, a data area
342
, a management (domain) area
343
, and a redundant area
344
. The redundant area
341
includes a non-defective sector as an alternative to a defective sector of a plurality of row sectors arranged in a row direction of the data area
342
. The row sector means a “block” comprising a plurality of memory cells connected to one word line among a plurality of word lines arranged in a row direction of the data area
342
. The data area
342
includes a plurality of memory cell which are arranged like an array in a row direction and a column direction.
The management area
343
holds information as to which of the plurality of sectors of the data area
342
is a defective sector. The redundant area
344
includes a non-defective sector as an alternative to a defective sector of a plurality of column sectors arrayed in a column direction of the data area
342
. The column sector means a “block” comprising a plurality of memory cells connected to one bit line of a plurality of bit lines arranged in a column direction of the data area
342
.
When a row sector of the data area
342
designated by a row address decoding a row address signal is a defective sector, the redundant circuit
310
selects a non-defective sector from the redundant area
341
as an alternative to the defective sector.
The row decoder
320
decodes a row address signal inputted from an external element, and then, outputs the decoded row address to the redundant circuit
310
and the word line driver
330
.
The word line driver
330
activates a row sector designated by the row address from the row decoder
320
. Further, the word line driver
330
selects a non-defective sector from the redundant area
341
as an alternative to the defective sector of the data area
342
on the basis of a selecting signal from the redundant circuit
310
.
The read/write circuit
350
reads and writes a data to a memory cell designated by a word line and a bit line.
Referring now to
FIG. 8
, the redundant circuit
310
is composed of spare decoders
311
and
312
, and an AND gate
313
.
FIG. 8
shows the case where two non-defective sectors
3411
and
3412
is included in the redundant area
341
. The spare decoders
311
and
312
decode address signals X
0
to Xn, and then, when the decoded row address is a defective sector, inactivates all of a plurality of the sectors included in the data area
342
while outputting an L (logical low) level or H (logical high) level signal in order to activate a non-defective sector of the redundant area
341
as an alternative to the defective sector. For example, when selecting the non-defective sector
3411
, the spare decoder
311
outputs an L level signal; on the other hand, the spare decoder
312
outputs an H level signal. In this case, these spare decoders
311
and
312
output an H level signal when a sector designated by the address signals X
0
to Xn is a non-defective sector.
The AND gate
313
operates a logical product of the L level signal or H level signal outputted from the spare decoders
311
and
312
.
The row decoder
320
includes NAND gates
321
to
32
n
and inverters
351
to
35
n
. These inverters
351
to
35
n
invert the address signals X
0
to Xn, respectively. Each of the NAND gates
321
to
32
n
operates a logical product of an output signal of the AND gate
313
and a logical product of two signals selected from the address signals X
0
to Xn and /X
0
to /Xn, and then, outputs an inverted signal of the operation result.
The word line driver
330
includes inverters
328
,
329
and
331
to
33
n
. The inverters
328
and
329
receive output signals from the spare decoders
311
and
312
, and then, selectively activate two non-defective sectors
3411
and
3412
included in the redundant circuit
341
. Moreover, Each of inverters
331
to
33
n
receives each output signal from the NAND gates
321
to
32
n
, and then, selectively activates a sector of the corresponding data area
342
.
The memory cell
340
includes a plurality of memory cells which are arranged like an array of m row x n column.
When the memory cell
3421
of the data area
342
is defective, a sector
3422
becomes a defective sector. Therefore, when address signals X
0
to Xn and /X
0
to /Xn designating the defective sector
3422
are inputted, the spare decoders
311
and
312
output a signal for selecting the sector
3411
of the redundant area
341
as an alternative to the defective sector
3422
. More specifically, the spare decoder
311
outputs an L level signal; on the other hand, the spared decoder
312
outputs an H level signal.
Whereupon the AND gate
313
outputs an L level signal to the NAND gates
321
to
32
n
of the row decoder
320
. Each of the NAND gates
321
to
32
n
necessarily outputs an H level signal because an L level signal is inputted from the AND gate
313
although two H level signals are inputted for designating a sector from the address signals X
0
to Xn and /X
0
to /Xn. Each of inverters
331
to
33
n
of the word line driver
330
receives an H level signal from the NAND gates
321
to
32
n
, and then, outputs an L level signal so as to activate the corresponding sector. Namely, when the address signals X
0
to Xn and /X
0
to /Xn designating the defective sector
3422
are inputted, all sectors of the data area
342
are inactivated.
On the other hand, the inverter
328
of the word line driver
330
receives an L level signal from the spare decoder
311
, and then, outputs an H level signal so as to activate the non-defective sector
3411
. Moreover, the inverter
329
receives an H level signal from the spare decoder
312
, and then, outputs an L level signal so as to inactivate the non-defective sector
3412
. By doing so, a non-defective sector
3412
of the redundant area
341
is selected as an alternative to the defective sector
3422
of the data area
342
. Then, a bit line corresponding to a column address decoded by a column decoder (not shown) is activated, and then, the read/write circuit
50
writes, reads and erases a data to each of n memory cells connected to the non-defective sector
3411
.
In the non-volatile semiconductor memory device
300
, as shown in
FIG. 9
, the data area
342
is divided into blocks BLK
1
to BLKr including a predetermined number of row sectors, and then, write, read and erase of data are carried out using blocks BLK
1
to BLKr as a management unit. Each of blocks BLK
1
to BLKr includes 8 sectors, for example.
The above method of using the blocks BLK
1
to BLKr as a management unit is called as an MGM (Mostly Good Memory) method. This MGM method is a method of making usable non-volatile semiconductor memory device even if all of blocks BLK
1
to BLKr are not composed of a non-defective sector. More specifically, according to the MGM method, the non-volatile semiconductor memory device is usable in a manner that even if a defective sector is included in one block, an access is made to a non-defective sector as an alternative to the defective sector. Namely, as described above, the non-volatile semiconductor memory device is usable in a manner that an access is made to the non-defective sector
3411
of the redundant area
341
as an alternative to the defective sector
3422
of the data area
342
.
However, as shown in
FIG. 9
, in the case where blocks BLK
3
, BLK
6
and BLKr-
4
of the data area
342
include a defective sector, according to the aforesaid MGM method, these blocks make a logical arrang
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
Yoha Connie C.
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