ESD protection circuit

Details ESD protection circuit ESD protection circuit

2000-08-18

2003-10-07

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S056000, C361S111000

Reexamination Certificate

active

06631059

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an ESD(Electro Static Discharge) protection circuit, and more particularly, to an ESD protection circuit which can effectively protect a product with three or two leveled electrodes in any cases when an external (+) or (−) ESD charge flows into the product.
2. Background of the Related Art
A related art ESD protection circuit will be explained with reference to the attached drawings.
FIG. 1
illustrates a circuit diagram showing a related art ESD protection circuit. Referring to
FIG. 1
, the related art ESD protection circuit has two MOS transistors TR
1
and TR
2
, wherein the first MOS transistor is a field MOS transistor TR
1
and the second MOS transistor is an active MOS transistor TR
2
. The field MOS transistor TR
1
has a gate and a source connected to one pad PAD
1
in common, and the active MOS transistor TR
2
has a gate connected to the ground GND and a source connected to one pad PAD
1
. And, drains of the field MOS transistor TR
1
and the active MOS transistor TR
2
are connected in together. The unexplained ‘A’ represents a discharge path of a (+) ESD charge flowing into the PAD
1
, and ‘B’ is a discharge path of a (−) ESD charge flowing into the PAD
1
. In a case when a (+) or (−) ESD charge flows from the PAD
1
to the PAD
2
, two transistors identical to the ones connected to the PAD
1
, i.e., a field MOS transistor TR
3
and an active MOS transistor TR
4
, are provided. In the aforementioned ESD protection circuit, when a (+) ESD charge flows from PAD
1
to PAD
2
, the (+) ESD charge flows to the ground terminal GND via the field MOS transistor TR
1
having a gate and a source connected to the PAD
1
, and is discharged to the PAD
2
via the active MOS transistor TR
4
having a source connected to the PAD
2
. And, when a (−) ESD charge flows from PAD
1
to PAD
2
, the (−) ESD charge flows to the ground terminal GND via the active MOS transistor TR
2
having a source connected to the PAD
1
, and is discharged to the PAD
2
via the field MOS transistor TR
3
having a gate and a source connected to the PAD
2
. Thus, the related art ESD protection circuit is comparatively strong against (+)(−) ESD charge.
However, the aforementioned related art ESD protection circuit has the following problems.
First, application to a device with three leveled electrodes(−, +and GND), such as CCD(Charge Coupled Device), is not possible, and adjustment of a threshold voltage Vt of the field transistor to a voltage higher than 15 V is difficult for a case the ESD protection circuit should be operative at a voltage higher than 15 V.
Second, since an inversion layer of the MOS(Metal Oxide Semiconductor) is used, the current flows through a surface, rather than bulk.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an ESD protection circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an ESD protection circuit which can protect a product with three leveled electrodes, such as a CCD, or two leveled electrodes, such as DRAM, in any case when an external (+) or (−) ESD charge flows in.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the ESD protection circuit for a product with three leveled electrodes(VP, VDD and GND) includes a first conduction type bipolar transistor and a second conduction type bipolar transistor connected in parallel between an input terminal and a GND, wherein the first conduction type bipolar transistor has a base terminal with a VP voltage applied thereto and the second conduction type bipolar transistor having a base terminal with a VDD voltage applied thereto, and collectors and emitters thereof connected to the input terminal or the GND.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4876620 (1989-10-01), Borkowicz
patent: 5291051 (1994-03-01), Hoang et al.
patent: 5304839 (1994-04-01), Chen et al.
patent: 5637900 (1997-06-01), Ker et al.
patent: 5889309 (1999-03-01), Yu et al.
patent: 5986867 (1999-11-01), Duvvury et al.

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