Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-08-11
2003-04-22
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C257S747000, C257S758000, C257S762000
Reexamination Certificate
active
06551856
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for forming input/output pad redistribution on a semiconductor substrate and device formed and more particularly, relates to a method for forming copper pad redistribution in a flip chip that is compatible with copper dual damascene process and a flip chip package formed.
BACKGROUND OF THE INVENTION
In the fabrication of IC devices, semiconductor chips are frequently attached to other chips or other electronic structures such as a printed circuit board. The attachment of the chip can be accomplished by a wire bonding process or by a flip chip attachment method. In a wire bonding process, each of a series of I/O bump terminal on a chip that is built on an aluminum bond pad is sequentially bonded to the connecting pads on a substrate. In a flip chip attachment method, all the I/O bumps on a semiconductor chip are terminated with a solder material. For instance, a frequently used solder material is a lead-rich, i.e., 97% lead/3% tin high melting temperature solder alloy. In the bonding process, a semiconductor chip is flipped over with the solder bumps aligned and placed in a reflow furnace to effect all the I/O connections to bonding pads on a substrate.
A major processing advantage made possible by the flip chip bonding process is its applicability to very high density I/O connections and its high reliability in the interconnects formed when compared to a wire bonding process. Moreover, the wire bonding process also has limitations in the total number of I/O interconnections that can be made in high performance devices.
A limiting factor for using the flip chip bonding process is the fine pitch bonding pads that are frequently required for wire bonding on modern high density devices. For instance, in a high density memory device, bonding pads that are arranged along the periphery of the device may have a pitch, or spacing, as small as 100 &mgr;m. At such narrow spacing, it is difficult and costly to accomplish bonding to the pads by using solder bumps in a flip chip bonding technique, taken into consideration that solder bumps in this case are of low profile, making underfill process extremely difficult. Moreover, a high density substrate which is very costly is required for flip chip bonding a device with a fine pitch I/O.
In order to bond high density IC devices that have peripheral I/O bonding pads with small pitch, i.e., in the range of approximately 100 &mgr;m, an I/O redistribution process must first be carried out before the formation of the solder bumps. In an I/O redistribution process, the peripheral I/O bonding pads are redistributed by signal traces to area array I/O bonding pads.
In a typical example, an IC chip that is equipped with peripheral I/O bonding pads has a pitch between the pads as small as 100 &mgr;m. Through an I/O redistribution process, a multiplicity of connecting traces are formed to redistribute the peripheral bonding pads to area array bonding pads. It should be noted that the pitch between the area array bonding pads are greatly increased, i.e., to the extent of approximately four times the pitch between the peripheral bonding pads. The significantly larger pitch between the area array bonding pads allows flip chip bonding to be connected on a low cost substrate manufactured by traditional process. The I/O redistribution process used on modern high density IC devices is therefore an important fabrication step to first enable the device to be solder bumped and then bonding to another chip or to a printed circuit board in a flip chip process. The formation of the connecting traces between the various pairs of bonding pads enables the I/O redistribution process to be accomplished.
More recently, void-free and seamless conductors are produced by electroplating copper from plating baths that contain a variety of additives. The capability of the electroplating method to superfill structural features without leaving voids or seams is unique and superior to that of other deposition techniques. Electrolytic copper plating techniques used in damascene structures can be defect-free if a seed layer deposited is continuous and has a uniform thickness. The copper seed layer is typically deposited by a physical vapor deposition technique over a barrier layer that prevents diffusion of copper into the insulator such as Ta or TaN.
A Cu dual damascene process consists of the formation of trenches and vias in a dielectric material, which stops at an etch-stop layer. The vias and trenches are then filled with a metal stack containing a barrier layer followed by Cu, and then removing the excess metal from the filled region typically by chemical mechanical polishing. This process can be used to form a single or a dual damascene structure. When Cu damascene interconnects are produced using plated Cu, typically a seed layer is sputtered on a barrier layer to improve the substrate conductivity and to allow for uniform Cu plating.
A conventional bond pad structure is shown in
FIG. 1
for a wire bonding package. In this conventional structure, a dual layer passivation structure of an undoped silicate gas (USG) layer
12
and a silicon nitride layer
14
is first deposited on a copper bond pad
20
. An opening is then formed in the passivation layers
12
,
14
for an aluminum/copper pad
18
. Several processing drawbacks are associated with this bond pad forming process, for instance, an additional 1~2 photomasking processing are required, a copper oxidation problem, and a large flat silicon nitride passivation layer which presents peeling problem due to built-in stress.
FIG. 2
illustrates a conventional method for wire redistribution in a flip tip package
30
. In the flip chip
30
, aluminum bond pad
16
is first formed on a silicon substrate
22
. After an oxide passivation layer
24
and a polyimid layer
26
are deposited on top of the aluminum bond pad
16
, an opening is formed for aluminum sputtering a redistribution layer, a second polyimide dielectric layer
32
is then deposited to insulate the aluminum wiring
28
. At an opposite end of the aluminum wiring
28
, an opening is formed for depositing an under-bump-metallurgy layer
34
, and a solder bump for forming solder ball
36
after a reflow process. In this conventional aluminum pad redistribution process for the flip chip package
30
, after the formation of the aluminum pad
16
and the deposition of the polyimide layer
26
, a first photomasking step is required such that etching can be carried out for forming the opening in the polyimide. After aluminum is sputtered for the aluminum wiring
28
for redistribution, a second photomasking step and subsequent etching are carried out to define the aluminum wiring. After a second polyimide layer
32
is deposited on top of the package
30
, a third photomasking and etching steps are required for the opening in polyimide layer
32
and for the growth of UBM layer
34
. The conventional aluminum pad redistribution process for the flip chip package therefore requires additional three photomasking steps which presents a major disadvantage for the process. While the process has been used and is compatible with aluminum process, there has been no pad redistribution process proposed that is compatible with a copper dual damascene process for forming pad redistribution. Since wet etching of copper is not possible, copper cannot be used to easily replace aluminum in a typical aluminum process which requires wet etching to define the redistribution.
It is therefore an object of the present invention to provide a flip chip pad redistribution process that does not have the drawbacks or shortcomings of the conventional pad redistribution process for aluminum.
It is another object of the present invention to provide a flip chip pad redistribution process that is compatible with a copper dual damascene process.
It is a further object of the present invention to provide a flip chip pad redistribution process wherein a redistribution pattern and a passivation pattern can be carried out on the same
Ha Nathan W.
Pham Long
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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