Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2001-11-19
2003-04-22
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230030, C365S230080, C365S233500, C365S236000
Reexamination Certificate
active
06552956
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having a plurality of operation modes, each operated with its inherent operation speed. More particularly, it relates to a semiconductor memory device and non-volatile semiconductor memory device that conduct successive operations by generating addresses subsequently among different operation modes.
2. Description of Related Art
Recent years, there have been popularized semiconductor memory devices that have a plurality of operation modes, each operated with its inherent operation speed. To be specific, the operation modes are classified into: readout operation; write operation; and erase operation. The readout operation is conducted at high-speed whereas the write and erase operations take much longer than the readout operation because the latter two operations accompany materialistic operations such as charge-injection to a floating gate and charge-emission from there. As semiconductor memory device having a plurality of operation modes among which operation speeds differ significantly, non-volatile semiconductor memory devices such as flash memory have been widely used for portable appliances.
Flash memory has conventionally been used as a device to record comparatively small volume of information such as memory of operational conditions for portable appliance or memory of concise information such as personal notes for user. Therefore, readout and write operations are united to be single operation such that input and output of data is made for single memory cell corresponding to an address given from the external. The operational specification is designed to be compatible with asynchronous static RAM (referred to as SRAM herein after). Erase operation can apply to pluralities of memory cell during one operational cycle. However, similar to readout and write operations, each cycle of erase operation goes in asynchronous with other operation modes.
On the other hand, portable appliances these days are required to handle even larger volume of information at high-speed, for example, transmission and receipt of image information by a cellular phone. Therefore, for system of portable appliances, there have been studied specifications having affinity with synchronous dynamic random access memory (SDRAM hereinafter) that operates in synchronous with system clock. Along with the trend, a flash memory is also required to have an operation mode such as burst operation that is compatible with system for SDRAM and changes addresses incessantly. In a word, there has been required a synchronous flash memory.
In design of synchronous flash memory, it is conceived to use structure of SDRAM. That is, provided that an address taken from the external is regarded as a start address, it is conceived of a synchronous flash memory provided with an address counter for counting up an address value in synchronous with a system clock, a control counter for counting burst values and the like.
However, speed of readout operation for a flash memory is determined by electric transmission delay due to its circuit structure. On the other hand, speed of write operation takes significantly longer than that of electric operation speed. This is because data is written in accordance with physical phenomenon called avalanche-breakdown phenomenon caused by high-field application of charges, whereby charges are injected to a floating gate of memory cells to write data. Similar to write operation, speed of erase operation takes significantly longer than that of electric operation because data is erased in accordance with physical phenomenon called tunneling caused by high-field application of charges, whereby charges are emitted from the floating gate of memory cells to erase data. Since the above-described operations are conducted with different mechanism, speeds of the respective operations differ. For example, as for flash memory MBM29LV800TA/BA-70, product of FUJITSU LIMITED, readout operation takes 70 n sec. at maximum as address access time (tACC) whereas program duration (tWHWH1) as write operation time takes 8 &mgr;sec. as standard value and sector-erase duration (tWHWH2) as erase operation time takes 1 sec. as standard value. Speeds of the respective operation modes thus differ significantly. To make comparison with an SDRAM that has only two operation modes, namely, readout and write modes, and speed levels of the two operation modes are generally same, which derives from electric transmission delay due its circuit structure, the flash memory has at least three operation modes and each of the operation modes works along different mechanism. Therefore, it is not feasible that each operation mode of a flash memory makes use of SDRAM circuit structure to realize optimal operation for respective operation modes. This is a problem conventional flash memory faces.
The problem such as the above will be described by referring to
FIG. 6
that shows a timing chart regarding burst operation of a flash memory. In
FIG. 6
, operation condition is set to: burst length=2; write (program) latency=0; and readout latency=2. In synchronous with an external clock signal CLK, a write (program) command PGM is received for Bank A designated by a bank address (Bank Add). PA
0
, a reference address of an external address (External Add.) is received for the write (program) command PGM. Further on, 2-bit write (program) data D
0
and D
1
are inputted in synchronous with each cycle of the external clock signal CLK. During a cycle of the clock signal CLK where the write (program) command PGM is inputted, the external address PA
0
is set in an address counter as an internal address (Internal Add.). Based on the internal address (Internal Add.), writing (programming) of data D
0
in the address PA
0
is started. Since write (program) operation is conducted in accordance with the as-mentioned physical phenomenon, including verify operation for verifying completion of correct data-write, it takes long to complete the write (program) operation. After the write (program) operation completes, the address counter makes an increment in the number of address from PA
0
to PA
1
so as to start writing (programming) data D
1
for a new address PA
1
.
Let us take a case wherein a readout command READ for a Bank B is received in synchronous with an external clock signal CLK to start burst readout operation at time t
0
when write (program) operation is being conducted. The bank B is designated by the bank address (Bank Add.) and the readout command READ is a command whose reference address is an external address (External Add.) RA
0
. Since speed of the readout operation is determined by electric transmission delay due to its circuit structure, data can be outputted in the same manner as operation of SDRAM. However, a cycle of write (program) operation is longer than that of readout operation and cycle lengths of these two operation cycles are great difference, write (program) operation and readout operation cannot share and use one address counter subsequently like bust operation in a conventional SDRAM. That is, since write (program) operation to an address PA
1
has not finished at time t
0
, in case burst-readout operation is inserted, write (program) operation must be suspended and resumed after completion of readout operation so as to avoid a scramble for an address of the address counter. Specifically, in order to stop write (program) operation temporarily, there are needed operations to: stop write (program) operation; drive out a write (program) address from the address counter or record the address driven out in there; drive out a burst value from a control counter or record the valve driven out in there; take a reference address into the address counter for burst-readout operation; set a burst value in the control counter during burst-readout operation and the like. Numbers of operations just for stopping write (program) operation temporarily make the operation system complicated, which is problema
Arent Fox Kintner & Plotkin & Kahn, PLLC
Elms Richard
Fujitsu Limited
Nguyen Van-Thu
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