Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-10-04
2003-11-18
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S530000, C257S758000, C257S759000
Reexamination Certificate
active
06649997
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device having a multi-layered wiring structure formed by sequentially laminating a wiring layer and an inter-layer insulation film on a semiconductor substrate and fuses or anti-fuses incorporated into the multi-layered wiring structure.
It becomes impossible to require that the whole chip can be made free from any defect as the integration density of the semiconductor memory becomes higher and the memory capacity thereof is increased. To this end, a method for compensating for a defective cell by use of a spare cell of a redundancy circuit previously formed is widely used in a memory LSI or an LSI having a memory mounted thereon. In order to use the spare cell instead of the defective cell, the memory is constructed such that, generally, the address of the defective cell detected and stored by use of a tester and then a fuse formed in the wiring layer made of polysilicon or aluminum is cut off by use of laser or an anti-fuse is connected by use of laser so as to permit the spare cell to be used instead of the defective cell.
However, since laser of a certain amount of energy is required to cut off the fuse or connect the anti-fuse by use of laser, a wiring or semiconductor element may be greatly damaged if it is formed below the wiring layer in which the fuse or anti-fuse is formed. Therefore, the wiring or semiconductor element cannot be formed below the fuse or anti-fuse forming layer. This is also an obstacle to further enhancement of the integration density of the LSI.
If the uppermost aluminum wiring can be used as the wiring layer to be used as the fuse or anti-fuse, it is generally convenient in the process since laser can be directly applied to the uppermost aluminum wiring layer. However, since the uppermost aluminum wiring is generally formed with a film thickness of one micron or more to reduce the resistance thereof and is made extremely thicker than the other wiring layer whose film thickness is 0.6 micron or less, it is required to use laser of large energy in order to cut off the fuse if the uppermost aluminum wiring is used as the fuse. In this case, a wiring or semiconductor element cannot be formed below the fuse formed layer and enhancement of the integration density cannot be expected. The same problem occurs in the case of anti-fuse.
An object of this invention is to provide a semiconductor device having a multi-layered wiring structure in which the number of manufacturing steps can be suppressed, the integration density can be enhanced and the desired characteristics can be maintained after cut-off of the fuse or connection of the anti-fuse is performed while wiring layers or elements formed below fuses or anti-fuses can be made free from an influence caused by the application of laser at the time of cut-off of the fuse or connection of the anti-fuse.
BRIEF SUMMARY OF THE INVENTION
A semiconductor device of this invention comprises a semiconductor substrate and a multi-layered wiring structure formed on the semiconductor substrate,
wherein the multi-layered wiring structure includes wirings having fuses or anti-fuses formed in a first wiring layer and a dummy pattern or patterns formed of a metal laminated film formed in a second wiring layer directly below the first wiring layer in which fuses or anti-fuses are formed.
Further, a semiconductor device of this invention comprises a semiconductor substrate, a multi-layered wiring structure formed on the semiconductor substrate and a passivation film formed on the multi-layered wiring structure, wherein the multi-layered wiring structure has a wiring including fuses or anti-fuses formed in a predetermined wiring layer and windows having openings formed above the fuses or anti-fuses, and the dummy pattern has an area which is not larger than an area of the window.
With the above structure, since laser energy applied for cut-off of the fuse or connection of the anti-fuse is effectively absorbed by the dummy pattern formed directly below the fuse or anti-fuse, wirings or semiconductor elements can be formed below the dummy pattern, the number of manufacturing steps will not be increased, the integration density can be enhanced and the stable operation can be attained even after cut-off of the fuse or connection of the anti-fuse.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
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Japanese Patent Office “Notification of Reasons for Rejection”, Mailing No. 163986, May 28, 2002.
Ha Nathan W.
Kabushiki Kaisha Toshiba
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