Transistor level circuit simulator using hierarchical data

Details Transistor level circuit simulator using hierarchical data Transistor level circuit simulator using hierarchical data

1999-05-07

2003-06-10

Jones, Hugh (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S015000, C703S016000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06577992

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer-aided design tools. More particularly, the present invention relates to the simulation of circuits using a hierarchical data structure and applying isomorphism matching to skip computations on duplicate subcircuit behavior.
2. Description of the Related Art
Device-level circuit simulation is an important step in microelectronic circuit design. Through such simulation, the functionality of a circuit may be validated and performance of the circuit may be predicted before the circuit is physically fabricated. The application of existing simulation tools such as SPICE, however, is limited to the simulation of small subcircuit blocks, typically less than 100,000 transistors, due to their memory capacity and performance limitations.
The capacity of existing simulators is primarily determined by the size of the circuit being simulated. Although circuits are hierarchically structured, the circuit hierarchy is typically flattened to the device level during simulation. As a result, the device connectivity and device parameters are stored during simulation for each device. This is particularly important since there is a fixed memory overhead measured in bytes per device. It follows that memory usage during circuit simulation is approximately proportional to the circuit size measured in number of devices in the circuit. In existing simulators, the memory usage per device is in the order of hundreds of bytes. This means that approximately 1 G bytes (one billion bytes) of memory are required in order to simulate a circuit containing 10 million devices, assuming 100 bytes of memory are required per device. The excessive memory usage therefore makes it impractical to use existing circuit simulators to perform full-chip circuit simulation on today's VLSI circuits. For example, a 256 M DRAM chip contains more than 256 million transistors and no existing circuit simulator can perform the full-chip simulation on the 256 M DRAM circuit. This memory limitation therefore forces microelectronic circuit designers to partition the full-chip design into blocks of smaller subcircuits which can be simulated by existing circuit simulators. Thus, the circuit is partitioned into subcircuits and the separate simulation results for the partitioned subcircuits are relied upon to predict the full-chip circuit behavior. However, the circuit partitioning is a tedious and error-prone task and thus reduces the designer's productivity. Moreover, the simulated subcircuit behavior obtained by local subcircuit simulation may be different from that obtained if the subcircuit is simulated together with all other subcircuits. Accordingly, it would be desirable if large microelectronic circuits could be simulated without such partitioning.
As described above, the size of the circuit that may be simulated using currently available circuit simulators is limited. However, even those circuits that can be simulated using currently available circuit simulators require a substantial amount of simulation time as well as memory. This becomes evident from the fact that the behavior of a circuit, as well as the behavior of each subcircuit, is formulated into a set of mathematical equations which are solved during simulation. Typically, the circuit hierarchy is flattened to the device level and numerical analysis is applied to the mathematical equations that are formulated from the flattened data. Since the mathematical equations are formulated at the device level, the computations required increase with the number of devices in the circuit. However, as described above, a large circuit may contain millions of devices and therefore the electrical behavior of the circuit may be expressed by millions of equations. As a result, the circuit can be time-consuming to simulate. Accordingly, the cost of testing such a circuit is non-trivial.
Although simulators having reduced simulation time have been developed, such improvements have generally been achieved through relaxing the accuracy of the simulation results. In addition, some simulators such as PowerMill available from Synopsys Inc., located in Mountain View, Calif. have achieved an increase in circuit simulation speed by taking advantage of circuit latency found in digital CMOS circuits. Thus, these simulators skip computations for idle subcircuits. However, the applicability of such simulators is limited to digital CMOS circuits. In addition, the assumption of circuit latency is getting invalidated by analog behavior arising in today's deep submicron technology. For example, due to noise from crosstalk capacitances, each device could be physically active all the time even though it is functionally idle most of the time. Therefore, although SPICE and other faster circuit simulators continue to play a critical role in microelectronic circuit simulation, the demand for more efficient circuit simulation is increasing.
To meet the challenge of simulating very large circuits containing millions of transistors, a simulation technology known as macromodeling has been implemented. Through the use of macromodeling, the electrical behavior of a subcircuit is characterized and the subcircuit is replaced by its behavioral model. Since this approach skips the details of a subcircuit and replaces it with an abstract model, the macromodeling approach consumes a minimal amount of memory. In addition, the simulation speed is much faster since it operates on a simpler behavioral description instead of massive numerical data. Theoretically, this approach can therefore be used to simulate a circuit of unlimited size. However, such approximate characterization of subcircuit behavior cannot accurately simulate the behavior of the entire circuit. Moreover, this approach requires a nontrivial effort to build the model since the modeling process is circuit dependent. Model characterization is tedious and time-consuming since it needs to include different combinations of input patterns and output load conditions. In addition, the subcircuit must be recharacterized whenever the subcircuit topology and circuit parameters change. Due to the difficulty in building the behavioral model, this macro-modeling approach is limited to applications where the subcircuit size is small or the subcircuit behavior is less sensitive to the surrounding environment. It would therefore be desirable if circuit simulation could be performed without such characterization.
In view of the above, it would be desirable if the simulation time and memory consumed during circuit simulation could be reduced. Moreover, a new technology is needed to allow a circuit simulator to perform full-chip simulation on circuits containing hundreds of million transistors, whether such circuits exist today or will emerge in the next decade.
SUMMARY OF THE INVENTION
The present invention implements methods and apparatus for validating the functionality and performance of microelectronic circuits prior to fabrication. More particularly, the present invention may be advantageously used to accurately simulate the electrical behavior of very large microelectronic circuits. This is accomplished, in part, through exploiting the hierarchical architecture in microelectronic circuit design.
Currently available circuit simulators have not used the hierarchical architecture of microelectronic circuits to benefit the simulation process. Rather, even when a hierarchical data structure is produced from a netlist representing the circuit being simulated, the hierarchical data structure is typically flattened during the simulation process. In other words, the memory required during simulation is proportional to the number of devices in the circuit being simulated. Similarly, the number of computations performed during the simulation process increases with the number of devices in the circuit. In order to reduce the simulation time and memory required during simulation, the circuit is often partitioned. However, such partitioning can introduce errors into the simula

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