Electrical computers and digital processing systems: processing – Processing architecture
Reexamination Certificate
2000-01-04
2003-09-30
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
C708S513000
Reexamination Certificate
active
06629231
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to processing systems and, more specifically, to a microprocessor having a floating point unit capable of converting numbers between scalar and SIMD values.
BACKGROUND OF THE INVENTION
The demand for ever-faster computers requires that state-of-the-art microprocessors execute instructions in the minimum amount of time. Microprocessor speeds have been increased in a number of different ways, including increasing the speed of the clock that drives the processor, reducing the number of clock cycles required to perform a given instruction, implementing pipeline architectures, and increasing the efficiency at which internal operations are performed. This last approach usually involves reducing the number of steps required to perform an internal operation.
Efficiency is particularly important in the floating point unit of a microprocessor. In floating point representation, every number may be represented by a significand (or mantissa) field, a sign bit, and an exponent field. Although the size of these fields may vary, the IEEE-754 standard defines the most commonly used floating point notation and forms the basis for floating point units (FPUs) in x86 type processors. The IEEE-754 standard includes a single precision format, a single extended precision format, a double precision format, and a double extended precision format. Single precision format comprises 32 bits: a sign bit, 8 exponent bits, and 23 significand bits. Single extended precision format comprises 44 bits: a sign bit, 11 exponent bits, and 32 significand bits. Double precision format comprises 64 bits: a sign bit, 11 exponent bits, and 52 significand bits. Double extended precision format comprises 80 bits: a sign bit, 15 exponent bits, and 64 significand bits.
It can be advantageous in a load-store implementation of IEEE-754 to represent all numeric values contained in the register file in the floating point unit as properly rounded values in a proprietary internal format with range and precision exceeding the widest. supported IEEE-754 format parameters. One such proprietary format is disclosed in U.S. patent application Ser. No. 09/377,140, entitled “Formatting Denormal Numbers for Processing in a Pipelined Floating Point Unit,” which is commonly assigned to the assignee of the present application. The disclosure of Application Serial No. 09/377,140 is hereby incorporated by reference into the present disclosure as if fully set forth herein. The internal proprietary format disclosed in U.S. patent application Ser. No. 09/377,140 comprises 93 bit: a sign bit, 17 exponent bits, and 70 significand bits, and a 5 bit tag field.
In some applications, it may be advantageous to utilize the internal proprietary format to store denormal values from single, double, or any precision with lesser range, as normal values in the extended range provided by this internal format. In “normal” floating point representation, it is assumed that the leading binary digit in the significand is always equal to 1. Since it is known to be equal to 1, the leading binary digit of the significand may, in some floating point representations, be omitted and the exponent value adjusted accordingly. Denormal values are ones which cannot be represented in normalized form (i.e., having the smallest possible exponent with a significand that is non-zero).
If an internal proprietary format is used to store denormal values as normal values in the extended range provided by the internal format and the register file of the FPU is also used to store single instruction-multiple data stream (SIMD) values SIMD implementation of integers (e.g., Intel MMX format) and to store IEEE-754 values (e.g., Intel streaming system extension (SSE) or AMD 3D-Now!), then a problem may occur if SIMD instructions are allowed to reference the results of scalar IEEE-754 instructions directly via the register file, without storing the scalar results to memory. The problem may occur because denormal IEEE-754 results are stored in the register file in normalized form, and that becomes visible to the SIMD instruction stream, which typically occupies the significand portion of the scalar IEEE-754 format(s). The programmer of the SIMD instruction stream (human or compiler) may be unaware of this non-standard but equivalent method of representing denormal numbers as normal within the CPU and therefore may not account for it in the SIMD program. This may produce non-equal and, possibly, incorrect results.
Therefore, there is a need in the art for improved microprocessor designs that are capable of converting denormal number representations between scalar and SIMD formats. More particularly, there is a need in the art for an improved floating point unit that provides an efficient conversion in the register file of denormal numbers between scalar and SIMD formats.
SUMMARY OF THE INVENTION
The limitations inherent in the prior art described above are overcome by the present invention which provides an improved pipelined floating point unit. In an advantageous embodiment of the present invention, the pipelined floating point unit comprises: a) a first plurality of pipelined functional units capable of processing operands conforming to a single instruction-multiple data stream (SIMD) instruction set architecture (ISA); b) a second plurality of pipelined functional units capable of processing operands conforming to a scalar instruction set architecture (ISA); and c) a first format fault detection circuit associated with at least one of the first plurality of pipelined functional units capable of determining whether a first operand is a denormal number and, in response to the determination, generating a first fault signal.
According to one embodiment of the present invention, the first fault signal causes a number conversion circuit associated with the pipelined floating point unit to modify a significand and an exponent of at least one operand in a data register associated with the pipelined floating point unit to thereby convert the at least one operand to a denormal number.
According to another embodiment of the present invention, the first format fault detection circuit determines the first operand is denormal by examining a tag field associated with the first operand.
According to still another embodiment of the present invention, the first format fault detection circuit further determines the first operand is denormal by determining if a most significant bit (MSB) of the first operand is set to Logic 1.
According to yet another embodiment of the present invention, the pipelined floating point unit further comprises a second format fault detection circuit associated with at least one of the second plurality of pipelined functional units capable of determining whether a second operand is a denormal number and, in response to the determination, generating a second fault signal.
According to a further embodiment of the present invention, the second fault signal causes a number conversion circuit associated with the pipelined floating point unit to modify a significand and an exponent of at least one operand in a data register associated with the pipelined floating point unit to thereby convert the at least one operand to a denormal number.
According to a still further embodiment of the present invention, the second format fault detection circuit determines the second operand is denormal by examining a tag field associated with the first operand.
According to a yet further embodiment of the present invention, the second format fault detection circuit further determines the second operand is denormal by determining if a most significant bit (MSB) of the second operand is set to zero.
According to another embodiment of the present invention, the second format fault detection circuit is further capable of determining whether the second operand is encoded as a single instruction-multiple data stream (SIMD) number and, in response to the determination, generating the second fault signal.
According to yet another
Coleman Eric
National Semiconductor Corporation
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