Semiconductor memory device and method of operating the same

Details Semiconductor memory device and method of operating the same Semiconductor memory device and method of operating the same

2001-11-13

2003-09-09

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S218000, C365S185190, C365S185270

Reexamination Certificate

active

06618292

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-345586, filed Nov. 13, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor memory device and a method of operating the same. More particularly, the present invention relates to a NAND type EEPROM (electrically erasable programmable read only memory) in which each memory cell unit (NAND cell) is formed by serially connecting a plurality of memory cells in the column direction.
2. Description of the Related Art
EEPROMs are known as a type of semiconductor memory devices where data can be electrically rewritten. Of EEPROMs, NAND type EEPROMs have been attracting attention because they can be adapted to a high degree of integration.
Each of the memory cells of a NAND type EEPROM comprises a MOS transistor having a stack gate structure. The memory cells of each column are connected in series and any two adjacent memory cells, or MOS transistors, share a common source/drain to produce NAND cells. Then, such NAND cells are arranged in rows to form a NAND cell block. A plurality of NAND cell blocks are arranged in the column direction to produce a memory cell array.
The drains of the NAND cells of each column of a memory cell array are commonly connected to a bit line by way of a first selection gate transistor. Similarly, the sources of the NAND cells of each column are connected to a common source line (grounded) by way of a second selection gate transistor. On the other hand, the control gates of each memory cell of a plurality of NAND cells are commonly connected in the row direction to form word lines (control gate lines). Similarly, the gate electrodes of the first and second selection gate transistors are commonly connected to form selection gate lines.
The papers (1) and (2) listed below describe NAND type EEPROMs having such a configuration.
(1) K. -D. Suh et al., “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme”, IEEE J. Solid-State Circuits, Vol. 30, pp. 1149-1156, November 1995.
(2) Y. Iwata et al., “A 35 ns Cycle Time 3.3 V Only 32 Mb NAND Flash EEPROM”, IEEE J. Solid-State Circuits, vol. 30, pp. 1157-1164, November 1995.
Now, the configuration of a known NAND type EEPROM will be described in greater detail by referring to the accompanying drawing.
FIG. 12
of the accompanying drawing is a schematic circuit diagram of memory cell array of a known NAND type EEPROM, showing only a NAND cell block NCB thereof.
Referring to
FIG. 12
, a NAND cell block NCB comprises a plurality of NAND cell units NCY arranged in rows. Each NAND cell unit NCY has NAND cells NC. Each NAND cells NC is formed by a plurality of memory cells M. Each memory cell M comprises a MOS transistor having a stack gate structure. In other words, a number of MOS transistors are connected in series in such a way that any two adjacent MOS transistors share a common source/drain. NAND cells NC are formed in this way.
The drain of the MOS transistor located at an end of the NAND cells NC arranged in each row is connected to a selection gate transistor S
1
. Each of the selection gate transistors S
1
is connected to a bit line BLi (i=0, 1, 2, . . . ). The source of the MOS transistor located at the other end of the NAND cells NC arranged in each row is connected to another selection gate transistor S
2
. Each of the selection gate transistors S
2
is connected to a common source line SL.
The control gates of memory cell M of the NAND cells NC arranged in each row are commonly connected to a word line WLj (j=0, 1, 2, . . . ). The gate electrodes of the selection gate transistors S
1
are commonly connected to a selection gate line SSL. The gate electrodes of the selection gate transistors S
2
are commonly connected to another selection gate line GSL.
Normally, a plurality of NAND cell blocks NCB, each having a configuration as described above, are arranged in the column direction to produce a memory cell array. Note that each bit line BLi and each common source line SL are shared by a plurality of NAND cell block arranged in the column direction.
Each NAND cell block NCB operates as a smallest unit for erasing data. In other words, data are collectively erased on a NAND cell block by NAND cell block basis. The memory cells M connected to a selected word line WLj in a NAND cell block NCB are referred to as a page. In other words, a page provides a unit for reading and writing data.
If each memory cell M is an n-channel MOS transistor, an operation of erasing data, that of reading data and that of writing data proceed in a manner as described below.
The E type state and the D type state of an n-channel MOS transistor are made to correspond to respective binary numbers. The E state refers to a state where the threshold value of the transistor is positive when electrons are injected into the floating gate. The D type state refers to a state where the threshold value of the transistor is negative when electrons are ejected from the floating gate. For instance, the D type state may be defined as a “1” data holding state (erased state), whereas the E type state may be defined as a “0” data holding state (written state). Then, an operation of shifting the threshold value of the memory cell M holding a “1” data to the positive direction into a state where the memory cell M is holding a “0” data is defined as “a write operation”. On the other hand, an operation of shifting the threshold value of the memory cell M holding a “0” data to the negative direction into a state where the memory cell M is holding a “1” data is defined as “an erase operation”. The following description of the specification is based on the above definitions.
FIG. 13
of the accompanying drawing is a chart illustrating the bias voltage applied to a number of different parts of the selected NAND cell block (to be referred to simply as selected block hereinafter) NCB for an erase operation, a read operation and a write operation. Note that the memory cell M is an n-channel MOS transistor.
For a data erasing operation, OV is applied to all the word lines WLj of the selected block NCB. The selection gate lines SSL, GSL and the bit lines BLi are held to a floating (F) state. A high positive erase voltage Vera (e.g., a 21 V pulse voltage with a cycle period of 3 ms) is applied to the P-type well region (substrate) of the cell region. As a result, the erase voltage Vera is applied between the P-type well region and the word lines WLj. Then, the electrons in the floating gate are ejected into the P-type well region by the FN tunnel current. Thus, each of the memory cells M in the selected block NCB is brought to the erased state of holding a “1” data.
On the other hand, the potential of the word lines WLj of each unselected NAND cell blocks (to be referred to as unselected block hereinafter) NCB is raised by way of capacitive coupling of the word lines WLj in the floating state and the P-type well region. The capacitive coupling ratio will be computed from the capacitance connected to the word lines WLj that are in the floating state. As a matter of fact, the capacitance of the word lines that are made of polysilicon and that of the P-type well region is high relative to the total capacitance. Therefore, the FN tunnel current will be prevented from flowing. Additionally, the threshold voltage of each and every memory cell M in the selected block NCB is checked to see if it has fallen below −1 V, for example for the purpose of verifying the erase operation.
For a data read operation, 0 V is applied to the selected word line WLj. A certain intermediary voltage Vread is applied to all the unselected word lines WLj and the selection gate lines SSL, GSL. The intermediary voltage Vread is a voltage necessary for making the channel region electrically conductive without relying on the threshold value. The data read operation is carried out by re

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