Method and structure for supply gated electronic components

Details Method and structure for supply gated electronic components Method and structure for supply gated electronic components

2001-05-31

2003-09-23

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S544000

Reexamination Certificate

active

06624687

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to transistor devices and, more particularly, to low power and ultra-low power MOS devices including low power supply gating transistors.
BACKGROUND OF THE INVENTION
With the emergence of an electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation, a demand has arisen for low power and ultra-low power transistor components and systems. To meet this demand, devices are emerging which have extremely low threshold voltages. Low threshold voltage devices use less power for active operation and are typically faster. However, in addition to low active power usage, it is also important that the devices have very small power dissipation in a standby mode, i.e., that the devices have very small leakage currents and, therefore, use very little power in standby mode.
There are a number of factors that contribute to the magnitude of a transistor's threshold voltage. For example, to set a transistor's threshold voltage near zero, light doping and/or counter doping in the channel region of the transistor may be provided. Lowering the threshold voltage of a transistor typically decreases active power dissipation by permitting the same performance to be achieved at a lower supply voltage. However, lowering the threshold voltage of a transistor normally increases standby power dissipation by increasing transistor leakage current. Consequently, devices having low threshold voltages can leak so much current when their circuits are in a sleep or standby mode that the gains made by lowering the threshold voltage are outweighed by the power lost to leakage.
In the discussion that follows, an NFET is used as an example. However, those of skill in the art will readily recognize that a PFET will behave in essentially the same manner with reversed polarities. An NFET is therefore chosen for simplicity and to avoid detracting from the invention.
FIG. 1A
is a schematic representation of a typical transistor
101
having a drain
103
, a source
105
and a gate
107
. As is well known in the art, if transistor
101
is an NFET, then transistor
101
is typically in an “off” or “standby” condition when the voltage on gate
107
(Vg) is sufficiently below a threshold voltage (Vth). However, as is also well known in the art, even when transistor
101
is in the “off” or “standby” state, there is still a leakage current from drain
103
to source
105
.
FIG. 1B
graphically represents the curve
110
of the voltage between the gate and the source (Vgs), on the horizontal axis
115
, versus the log of the current between the drain and the source (Ids), on the vertical axis
117
, for a typical prior art standard CMOS NFET transistor. As seen in
FIG. 1B
, Ids has a minimal value
113
in portion
119
of curve
110
, as Vgs approaches zero volts and the transistor is driven into standby mode. However, Ids remains at minimal value
113
and is therefore typically never brought down to zero amps, even as Vgs goes negative. In portion
121
of curve
110
, Ids increases exponentially to point
111
when Vgs is equal to Vth. After Vth is reached, and the transistor is in active mode, Ids increases as a quadratic function along portion
123
of curve
110
and substantially levels off from point
125
forward.
In a typical standard CMOS NFET, the leakage current, i.e., the current at point
113
in
FIG. 1B
is on the order of one pico-ampere (10
−12
ampere) per micron. In addition, some newer transistors have 0.18-micron feature sizes and have leakage currents on the order of a nanoamp (10
−9
ampere) per micron. Consequently, devices including one hundred million of these new transistors and using a standard 1.8 volt supply voltage leak on the order of 0.1 ampere and dissipate 180 milliwatts of power in standby.
While the leakage currents discussed for standard CMOS transistors are less than ideal, they were largely tolerated in the prior art and, in standard CMOS, were not considered a fatal flaw. As discussed in more detail below, for low threshold transistors, leakage currents are not only significant but are a fatal flaw that can completely overshadow the advantages of these transistors and make them unworkable components.
Returning to the discussion of standard CMOS devices, if it were necessitated, one method to reduce the leakage current in standard CMOS would be to provide gating transistors to isolate the device from the voltage sources.
FIG. 2
shows a prior art supply gated device
200
including a device
201
, a first prior art gate transistor
203
, coupled between first supply voltage
207
and device
201
, and a second prior art gate transistor
205
, coupled between device
201
and a second supply voltage
209
. Device
201
could be any one of numerous devices well known to those of skill in the art such as a single transistor, an inverter, a latch, any one of several gates, or any other logic or memory devices. In
FIG. 2
, prior art gate transistor
203
is a PFET and includes a source
211
, a gate
213
and a drain
215
. Likewise, in
FIG. 2
, prior art gate transistor
205
is an NFET and includes a drain
221
, a gate
223
and a source
225
.
In standard CMOS, the difference in potential between first supply voltage
207
and second supply voltage
209
was on the order of two (2.0) volts. In one embodiment, first supply voltage
207
was a positive two-volt supply while second supply voltage
209
was ground, thus giving the typical two-volt differential.
The addition of prior art gating transistors
203
and
205
to device
201
helped control leakage current by providing a capability to isolate device
201
from first supply voltage
207
and second supply voltage
209
. This capability was provided by using prior art gating transistors
203
and
205
as switches controlled by a voltage supplied to gates
213
and
223
of prior art gating transistors
203
and
205
, respectively. Unfortunately, the addition of prior art gating transistors
203
and
205
meant that an additional transistor was added to each current path, i.e., prior art gating transistors
203
and
205
each added a resistance in series to the path between device
201
and the first and second supply voltages
207
and
209
, respectively. This added resistance meant decreased performance and decreased device speed. The performance reduction due to the addition of prior art gating transistors
203
and
205
could be partially offset by increasing the size of prior art gating transistors
203
and
205
relative to the size of the transistors making up device
201
. However, even a ten fold increase in relative size of prior art gating transistors
203
and
205
compared to the transistors in device
201
would still typically yield a decrease in performance of about ten percent for gated device
200
compared with a non-gated device.
A theoretical way to minimize the decrease in performance of device
201
due to the addition of prior art gating transistors
203
and
205
would be to drive prior art gating transistors
203
and
205
at a higher voltage than the voltage driving device
201
. However, in practice, to actually make any significant difference in the performance, i.e., to significantly decrease the resistance added by prior art gating transistors
203
and
205
, the supply voltages of prior art gating transistors
203
and
205
would need to be multiples, and preferable an order of magnitude, larger than the differential between first supply voltage
207
and second supply voltage
209
. However, as noted above, in standard 0.18 micron CMOS technology, the voltage differential between first supply voltage
207
and second supply voltage
209
is on the order of two volts, the maximum tolerated over time by the 36 angstrom gate oxide. Consequently, the voltage differential required to significantly decrease the added resistance of prior art gating transistors
203
and
205
could not be withstood by standard CMOS transistors over time and pri

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