Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-04-06
2003-04-22
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C148S033200, C148S033300, C216S002000, C216S039000, C216S079000, C216S099000, C438S734000, C438S745000, C438S753000
Reexamination Certificate
active
06551944
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a process for manufacturing a semiconductor material wafer comprising single-crystal regions separated by insulating material regions, in particular for manufacturing integrated power devices, and wafer thus obtained.
BACKGROUND OF THE INVENTION
As known, the integration of power devices with components of the control circuitry involves several problems mainly due to parasitic effects depending on undesired interactions between the power devices and the circuitry components. Conventionally, electrical isolation between various components produced on the same chip is obtained through reverse-biased PN junctions. Thereby parasitic components (such as diodes, transistors or capacitors) degrading the performance of the circuit also form besides the design components.
Parasitic elements are disadvantageously present in any type of integrated circuit, but are more problematic in power devices, and particularly the vertical current flow type. In fact, the problems caused by the parasitic components depends on the values of the operating currents and voltages and, in particular, the switching speed. Furthermore, with respect to lateral devices, the vertical current flow devices have a more complex structure, composed of many active layers, and it is therefore difficult to provide a physical/mathematical model taking parasitic effects into account.
Various solutions have been proposed to solve the above problem, some of which use insulating structures of the SOI (Silicon On Insulator) type.
Manufacturing SOI structures using the technique of wafer bonding or silicon direct bonding (SDB) is described, for example, in “Silicon-on-Insulator Wafer Bonding-Wafer Thinning Technological Evaluations”, by J. Hausman, G. A. Spierings, U. K. P. Biermnan and J. A. Pals,
Japanese Journal of Applied Physics,
Vol. 28, No. 8, August 1989, pp. 1426-1443 and in “Dielectric Isolation Technologies and Power Integrated Circuits”, Y. Sugawara, in
Smart Power ICs—Technologies and Applications,
by B. Murari, F. Bertotti, G. A. Vignola, Springer, 1995, pp. 150-157. Specifically, according to this technique, the surface of two silicon wafers is oxidized, and the two wafers are bonded together, to obtain a single wafer comprising a buried oxide layer. A surface of the thus obtained wafer is then ground to reduce the thickness thereof to a desired value (typically from a few tenths to a few tens of microns) and obtain a silicon layer for accommodating the circuit components. The silicon layer and, subsequently, the oxide layer are then selectively etched where power devices are to be formed. Epitaxial growth is then carried out, to obtain islands of buried oxide separated from each other by silicon continuity regions. Finally, the active areas (the regions over the buried oxide islands), are insulated by trenches filled with dielectric material and are used for the forming of low-voltage circuitry while power devices with vertical current flow are formed in the continuity regions of the silicon.
In a variant of the illustrated solution, the oxide islands are formed on one of the wafers prior to bonding.
The illustrated solutions are disadvantageous because of their complexity and the cost associated in particular with some phases, such as wafer bonding to form an SOI substrate. Furthermore, the variant above described has the drawback that bonding of wafers whose surfaces are not uniform (because of the presence of silicon regions and oxide regions) is a difficult process and has low yield.
To overcome these disadvantages, European patent application No. 98830007.5 of Jan. 13, 1998 filed in the applicant's name describes a method using conventional steps in microelectronics. Specifically, according to this method, initially a silicon wafer is recessed to form trenches having a first depth; the silicon portions adjacent to the trenches are protected with a hard mask shaped like an upturned U and the trenches are etched to a second depth. Columns or walls whose top end is protected by the hard mask formn in this way. The wafer is then oxidized and the portions of the columns or walls not protected by the hard mask form silicon oxide regions expanding towards the inside the trenches, closing them. In contrast, the top end of the columns or walls is not oxidized. Therefore, at the end of the oxidation a continuous silicon oxide layer, surmounted by single-crystal silicon regions, is obtained. Finally, using the silicon of the single-crystal silicon regions as nucleus, an epitaxial growth is carried out, forming a layer which can be used for integrating electronic components.
According to a different solution, described in European patent application No. 98830299.8 of May 15, 1998 in the same applicant's name, wells, of N
+
type for example, are formed in a substrate, of P type for example, by ion implantation; an epitaxial layer is then grown. Trenches extending as far as the buried wells, laterally thereto, are formed in the epitaxial layer; the buried wells are anodized, then oxidized and then removed, to create a buried air gap having above epitaxial regions of single-crystal silicon connected to each other and to the rest of the wafer by means of silicon columns. Thermal oxidation is then carried out, to grow an oxide region from the walls of the buried air gap and from the trenches, to fill the buried air gap and the trenches. At the end the epitaxial regions are completely surrounded by silicon oxide, both at the sides and at the bottom.
Finally, in European patent application No. 98830476.2 of Aug. 3, 1998 in the same applicant's name, the trenches are formed by two etching steps, firstly anisotropic and then isotropic, to widen the trenches and to reduce the thickness of the portions of the substrate to be oxidized to form the buried oxide region, before carrying out the epitaxial growth.
A drawback of the last three described solutions is that the oxide regions growing by virtue of thermal oxidation exert a pressure on the surrounding single-crystal silicon regions because of the different thermal expansion coefficients. Crystallographic defects may therefore form in the silicon; it is not possible to eliminate these subsequently and they compromise the quality of the end product.
SUMMARY OF THE INVENTION
The present invention provides a process for manufacturing an SOI substrate not affected by the described drawbacks and, in particular, of modest manufacture cost and high quality.
An embodiment of the present invention thus provides a method for manufacturing a wafer comprising first and second single-crystal regions insulated by insulating regions by carrying out a directional etching in a semiconductor material body to form trenches having a first width; carrying an isotropic etching through the trenches of the semiconductor material body under the trenches to form cavities having a second width larger than the first width; covering the walls of the cavities with dielectric material; and depositing non-conducting or poorly conducting material different from thermal oxide to at least partially fill the cavities so as to form a single-crystal island separated from the semiconductor material body.
REFERENCES:
patent: 5212109 (1993-05-01), Mihara
patent: 5641380 (1997-06-01), Yamazaki et al.
patent: 6075269 (2000-06-01), Terasawa et al.
patent: 2 156 149 (1985-10-01), None
patent: 03071651 (1991-03-01), None
patent: 08070112 (1996-03-01), None
patent: 0 059 796 (1982-09-01), None
patent: 0 191 476 (1986-08-01), None
patent: 0 223 694 (1987-05-01), None
S. Mukherjee, “Dieletric-Isolation based on high voltage IC process,” Dielectric Isolation and Silicon-on-Insulator Technologies: pp. 70-76.
Y. Sugawara, “Power DI-Ics developed since 1981 and their applications,” Dieletric Isolation Technologies and Power Ics: pp. 105-108.
y. Sugawara, “Increment techniques for electric power capibility,” Dieletric Isolation Technologies and Power Ics: pp. 150-157.
Y. Sugawara, “Comparison Between Bulk and SOI Processing,” SOI CMOS Technology: pp. 91
Fallica Piero Giorgio
Patti Davide Giuseppe
Rapisarda Cirino
Jorgenson Lisa K.
Powell William A.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tarleton E. Russell
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