Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated...
Reexamination Certificate
2001-01-05
2003-04-08
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
C257S797000, C257S401000
Reexamination Certificate
active
06545336
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device whose isolation regions are flattened by means of chemical-and-mechanical polishing (hereinafter called simply “CMP”) as well as to a method of manufacturing the semiconductor device.
2. Description of the Background Art
FIG. 6
is a plan view showing a semiconductor wafer processed according to a conventional manufacturing method. As shown in
FIG. 6
, reference numeral
10
designates an isolation region formed by means of the trench isolation technique. Reference numeral
12
designates active regions separated by the isolation region
10
.
FIG. 7
is a cross-sectional view for describing the conventional trench isolation technique for forming on a semiconductor wafer the isolation region
10
shown in FIG.
6
.
According to the trench isolation technique, a nitride film
16
is formed on a silicon layer
14
of the semiconductor wafer. Next, a trench
18
which is to become the isolation region
10
is formed in the silicon layer
14
and the nitride film
16
. Next, an oxide is deposited over the entire surface of a semiconductor wafer so as to be embedded in the trench
18
. Finally, undesired oxides are removed by means of CMP while the nitride film
16
is used as a stopper film. As a consequence, oxides remain only within the trench
18
, thus forming the isolation region
10
which separates the isolation regions
12
.
A CMP operation employed in the course of forming the isolation region
10
is performed on condition that an oxide film is abraded at a higher rate than is a nitride film. For this reason, a so-called dishing phenomenon arises in the isolation region
10
when the isolation region
10
occupies a comparatively large area of the semiconductor wafer, as shown in FIG.
7
.
If a dishing phenomenon arises in a specific isolation region
10
, intensive force arises in the active regions
12
adjoining the isolation region
10
. Consequently, the nitride film
16
covering the active regions
12
that undergo intensive stress is abraded much more than is the nitride film
16
covering other regions. As mentioned above, in a case where a large isolation region
10
is present, the structure of a conventional semiconductor device and the conventional trench isolation technique pose a problem of an active region being apt to vary in its finished state.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the foregoing problem and is aimed at providing a semiconductor device which prevents occurrence of variations in a finished state of active regions even in a case where a large isolation area is present.
The present invention is also aimed at providing a method of manufacturing a semiconductor device, which device prevents occurrence of variations in a finished state of active regions even in a case where a large isolation area is present.
The above objects of the present invention are achieved by . . . . The . . . includes.
The above objects of the present invention are achieved by . . . . The . . . includes.
REFERENCES:
patent: 6020616 (2000-02-01), Bothra et al.
patent: 6215197 (2001-04-01), Iwamatsu
patent: 6396158 (2002-05-01), Travis et al.
patent: 6414387 (2002-07-01), Hara et al.
patent: 6465290 (2002-10-01), Suguro et al.
patent: 11-330223 (1999-11-01), None
Kobayashi Hiromichi
Sasaki Takanori
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