Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2001-02-26
2003-08-05
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S185110, C365S185180, C365S185190, C365S185280, C365S185230
Reexamination Certificate
active
06603702
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor integrated circuit including a transistor designed to selectively provide either a low or a high voltage.
There has been the constraint imposed on the use condition of conventional MOS (metal-oxide semiconductor) transistors that the drain-source voltage Vds should not exceed a sustaining voltage Vds(sus), the reason for which is as follows. If Vds exceeds Vds(sus) when a drain-source current Ids is flowing, then avalanche breakdown occurs, resulting in a rapid increase in Id (the drain current). Vds(sus) is the voltage below the drain-source breakdown voltage BVds which is defined on the condition that the gate-source voltage Vgs is equal to 0 V. The breakdown voltage defined by Vds(sus) is called the “sustaining breakdown voltage”. Further, the same sustaining breakdown voltage constraint is imposed also on bipolar transistors.
FIG. 1
shows characteristics of an N channel MOS transistor by measurements at room temperature. The gate oxide film thickness, the gate length, and the BVds of the transistor are, 8 nm, 0.4 &mgr;m, and about 7 V, respectively. As can be seen from
FIG. 1
, the Vds(sus) of the transistor is 4.0 V.
FIG. 1
shows that if Vds increases beyond Vds(sus) when Vgs is held at, for example, 3.0 V, avalanche breakdown occurs and there is a sudden increase in Id. This phenomenon may be explained as follows. Electrons, i.e., carriers forming Ids, are accelerated by a high electric field at the drain end. The accelerated electrons generate an electron-hole pair by collision. The generated electron, accelerated with high energy, jumps into the gate oxide film. On the other hand, the generated hole is observed as a substrate current Isub superimposing Ids and there is appeared a sudden increase in Id (=Ids+Isub). Such a phenomenon is called the “hot carrier effect” which is a known cause of transistor reliability problems. Accordingly, the power supply voltage, when the transistor of
FIG. 1
is used, is limited to voltage values below Vds(sus), for example, 3.3 V. Also for the case of P channel MOS transistors, the hot carrier effect more or less exists, and the same as pointed out above for the N channel MOS transistor can be applied for the P channel MOS transistor.
Apart from the above, for example, in a flash memory of the floating gate type having nonvolatile memory cells, it is required that the wordlines be driven at a low voltage and at a high voltage. M. Hiraki et al. disclose, in their paper entitled “A 3.3V 90 MHz Flash Memory Module Embedded in a 32b RISC Microcontroller”, 1999 ISSCC Digest of Technical Papers, pp. 116-117, a flash memory technology in which a wordline driver of the low performance/high voltage specification for programming and erase operations is provided in addition to the provision of another wordline driver of the high performance/low voltage specification for read operations and either one of these wordline drivers is selectively used. The read wordline driver is formed of a low breakdown voltage MOS transistor whose gate oxide film is thin, whereas the programming/erase wordline driver is formed of a high breakdown voltage MOS transistor whose gate oxide film is thick.
However, the above-described conventional flash memory requires preparation of two different masks in order to realize two different gate oxide film thicknesses for the wordline drivers, therefore increasing production costs.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to allow even a low breakdown voltage transistor to handle not only low voltage but also high voltage without introducing any problems, in a semiconductor integrated circuit including a transistor designed to selectively provide either a low or a high voltage.
Another object of the present invention is to allow even a wordline driver of the low voltage specification to handle not only low voltage but also high voltage without introducing any problems, in a flash memory.
In order to provide a description of the concept of the inventor of the present invention, suppose here that a given power supply voltage is applied to a series circuit of an N channel MOS transistor of
FIG. 1 and a
P channel MOS transistor (not shown). Further suppose that the power supply voltage is above the Vds(sus) of the N channel MOS transistor. At this time, for example, if the N channel MOS transistor makes a state transition from the on state to the off state and the P channel MOS transistor makes a state transition from the off state to the on state, this may create, in the course of such state transition, a situation that there is a flow of Ids through the N channel MOS transistor and the Vds of the N channel MOS transistor exceeds Vds(sus). Under this situation, as described above, avalanche breakdown will occur and the Isub component which is a cause of the drop in reliability comes to be contained in Id. The inventor of the present invention gave attention to the fact that if Vgs is less than the threshold voltage of the N channel MOS transistor (for example, when Vgs=0 V and the N channel MOS transistor is “off”), Id does not increase even when Vds (=the power supply voltage) increases beyond Vds(sus), thereby maintaining the state that Id=0. Under this condition, Id=0, so that there are no carriers to be accelerated. Therefore, even when Vds increases beyond Vds(sus), no breakdown will occur until BVds is reached. Further, the inventor of the present invention gave attention to the following fact. That is, when Vgs is above the threshold voltage of the N channel MOS transistor (for example, when Vgs=3.0 V and the N channel MOS transistor is “on”), even if the power supply voltage increases beyond Vds(sus), most of the increased power supply voltage is applied to a load of the N channel MOS transistor (for example, the P channel MOS transistor in the off state) and the voltage that is applied between the drain and the source of the N channel MOS transistor does not increase beyond Vds(sus). Therefore, no avalanche breakdown occurs. In other words, as long as the logical state of the N channel MOS transistor is determined, no avalanche breakdown will occur even when the power supply voltage increases beyond Vds(sus). More concretely, for the case of the N channel MOS transistor of
FIG. 1
, since electric field application of as much as 8 MV/cm is tolerable for a short period of time, it is possible, in accordance with the present invention, to increase the power supply voltage above a voltage level above Vds(sus) (for example, about 6.4 V) in the case of employing the transistor.
From the above points to which the inventor of the present invention gave attention, the present invention provides a semiconductor integrated circuit comprising a transistor having a given sustaining voltage and a voltage control circuit for controlling a power supply voltage connected to the transistor, wherein the voltage control circuit operates to hold the power supply voltage at a voltage level below the sustaining voltage when the logical state of the transistor is changed, and operates to ramp up the power supply voltage from the voltage level below the sustaining voltage to a voltage level above the sustaining voltage after the logical state of the transistor has been changed. Moreover, before the logical state of the transistor is changed next, the voltage control circuit operates to ramp down the power supply voltage from the voltage level above the sustaining voltage to the voltage level below the sustaining voltage.
For example, when a MOS transistor is “on”, the rate at which the power supply voltage ramps up is limited in such a manner that the logical state of a next-stage transistor of the MOS transistor should not be changed by a change in the drain-source voltage of the MOS transistor due to the ramping up of the power supply voltage. Additionally, for example, when a MOS transistor is “on”, the rate at which the power supply voltage ramps down is limited in such a manner th
Matsushita Electric - Industrial Co., Ltd.
Pham Ly Duy
LandOfFree
Semiconductor integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3106923