Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-08-30
2003-07-08
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S014000, C438S107000, C438S112000, C438S127000, C438S460000, C716S030000, C716S030000
Reexamination Certificate
active
06589801
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, in general, to a method of manufacturing semiconductor packages, and more particularly, to a method of manufacturing chip-scale semiconductor packages at a wafer scale level using wafer mapping techniques that results in both improved production efficiencies and higher package yields.
2. Description of the Related Art
In response to the recent trend of electronic equipment toward devices that are lighter, thinner, smaller, and more compact, such as communication systems and computers, it has become necessary to reduce the size of semiconductor packages used in such equipment to that approaching the size of a single semiconductor chip, while at the same time achieving high performance chip packages having “super” input/output pin densities. Such requirements are met in a semiconductor package known in the art as a “chip-size semiconductor package” or “chip-scale semiconductor package.” In the following description, such packages are referred to as “chip-scale semiconductor packages” for ease of description.
FIG. 10
is a flowchart of a conventional method of manufacturing chip-scale semiconductor packages. As shown in the drawings, a wafer-shaped circuit substrate having a plurality of circuit pattern units in it is attached to a semiconductor wafer having a plurality of semiconductor chip units in it, with the substrate having a circuit pattern unit area of the same size and shape as that of the chip units in the wafer. This step is referred to as the “wafer lamination” step in the art.
After the wafer lamination step, a packaging process is performed on the laminated assembly. In a typical packaging process, a wire bonding step is first performed to electrically connect the semiconductor chip units of the wafer to corresponding ones of the circuit pattern units in the substrate. The wire bonding step is followed by an encapsulation step. In the encapsulation step, the wire-bonded parts are individually encapsulated within an envelope of an encapsulation material to form an encapsulated part that protects the wire-bonded parts from harmful environmental elements. Next, a solder ball welding step is performed in which a plurality of solder balls, which function as the signal and power input/output terminals of the packages, are welded to solder ball lands on the substrate.
A plurality of connected semiconductor package units are thereby formed in the laminated wafer-substrate assembly. After the above packaging process is complete, a “singulation” step is performed, in which the individual semiconductor package units of the wafer are “singulated,” i.e., separated from each other and the assembly, typically by means of process in which the wafer-substrate laminated assembly is cut through along the periphery of each individual semiconductor package. It is usually necessary thereafter to perform a marking step in which the singulated package units are first tested, and then marked with their quality and/or grade. The marking step typically completes the semiconductor package manufacturing process.
However, the conventional method described above has certain drawbacks associated with it. In particular, the method involves attaching a wafer to a circuit substrate “blindly,” i.e., without identifying defective chip units in the wafer and/or defective circuit pattern units in the substrate prior to effecting the packaging process. Therefore, the conventional method can result in a prodigal waste of expensive chips, circuit patterns, bonding wires, encapsulation materials, and solder balls, and needlessly consume expensive labor and time, in the completion of packages that are defective because of the presence of a defective chip and/or circuit pattern, thus resulting in low production yields and inefficient productivity.
Another problem experienced in the conventional method is the complexity caused by its need for a separate marking step in which the singulated package units are first tested at one station using a first piece of equipment, and then marked with quality and/or grade information at a second station and using a second piece of equipment.
Wafers can be tested and marked with quality and/or grade information in the form of, e.g., ink dots on each semiconductor chip unit before the wafers are subjected to the lamination step. However, this form of quality and/or grade marking is subsequently hidden from view by the circuit substrate during the lamination step, and it therefore becomes impossible to discriminate defective chip units from good units during the packaging process. Thus, even using marked wafers, the conventional method still results in inefficient waste of expensive bonding wires, encapsulation materials and solder balls and the needless consumption labor and time, thereby resulting in low production yields and efficiencies.
Additionally, in the conventional marking step, the individual semiconductor package units resulting from the singulation process are typically first placed on trays using a package “pick-and-place” device prior to being passed on to a separate marking device. The marking device marks product information, such as the product number, manufacturer, production date, and the like, in the form of alphanumeric characters on the lower surface of each package unit. In the case of chip-scale package units, the product information is marked on the lower surface of the chip of each package unit. Thus, the marking step in the conventional method necessitates two separate devices, each having a relatively complicated construction, one for picking and placing the packages on the trays prior to marking, and one for picking and placing the packages in designated attitudes and/or positions during the marking step. This separation of mechanical functions into two distinct operations and equipment also results in reduced production efficiency.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made with the above problems of the prior art in mind, and accordingly, provides a method of manufacturing chip-scale semiconductor packages that eliminates the packaging of defective chip and/or circuit pattern units, thereby improving production efficiency and yield.
The present invention also provides a method of manufacturing chip-scale packages in which the quality and/or grade of package units is marked on the packages in accordance with wafer and/or substrate pre-testing data, and in which defective packages are easily discriminated from good packages without the need for testing after package singulation, even though defective chip units and/or circuit pattern units may have been incorporated into the packages intentionally, thereby improving production efficiency and yield.
The present invention also provides a method of manufacturing chip-scale packages in which only “good” circuit pattern units of a circuit substrate are used, while defective pattern units from the substrate are eliminated, thereby making it possible to avoid the packaging of expensive, “good” chip units with defective circuit pattern units, thereby improving package production efficiency and yield.
The present invention further provides a method of manufacturing chip-scale packages in which both the package pick-and-place step and the package marking step are combined in a single device, thus simplifying the manufacturing process and improving production efficiency.
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DiCaprio Vincent
Kang Dae-Byung
Liebhard Markus K.
Park In-Bae
Yoon Ju-Hoon
Amkor Technology Inc.
Luu Chuong Anh
Skjerven Morrill LLP
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