Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-07-12
2003-06-03
Lam, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185330, C365S230060
Reexamination Certificate
active
06574148
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory devices and bit line drivers.
BACKGROUND OF THE INVENTION
Electrically erasable and programmable read only memories (EEPROMs) are reprogrammable non-volatile memories that are widely used in computer systems for storing data. The typical data storage element of an EEPROM is a floating gate transistor. The floating gate transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source and drain regions. Data is represented by charge stored on the floating gate and the resulting conductivity obtained between source and drain regions.
For example, a floating gate memory cell can be formed in a P-type substrate with an N-type diffused source region and an N-type drain diffusion formed in the substrate. The spaced apart source and drain regions define an intermediate channel region. A floating gate, typically made of doped polysilicon, is located over the channel region and is electrically isolated from the other cell elements by oxide. For example, a thin gate oxide can be located between the floating gate and the channel region. A control gate is located over the floating gate and can also be made of doped polysilicon. The control gate is separated from the floating gate by a dielectric layer.
To program a memory cell, a high positive voltage Vg, such as +12 volts, is applied to the control gate of the cell. In addition, a moderate positive voltage of about +5 volts is applied to the drain (Vd) and the source voltage (Vs) and the substrate voltage (Vsub) are at ground level. In prior memories, the power supply current requirements for the +12 volts applied to the control gate and the +5 volts applied to the drain region are in the order of a few hundreds of micro amps per cell being programmed. The small current requirement is due, in large part, to the fact that only a few flash cells are ever programmed at one time. Thus, these voltages can be generated on the integrated circuit utilizing charge pump circuitry that is powered by the primary supply voltage Vcc. The above voltage ranges are based upon the assumption that the primary supply voltage Vcc for the memory is +3 volts.
The above conditions result in the inducement of hot electron injection in the channel region near the drain region of the memory cell. These high-energy electrons travel through the thin gate oxide towards the positive voltage present on the control gate and collect on the floating gate. The electrons remain on the floating gate and function to increase the effective threshold voltage of the cell as compared to a cell that has not been programmed.
As memory cell population densities increase, the physical space allocated to device components decreases. For example, bit lines used to couple memory cells located in a column of the memory device may increase in length and decrease in width. These changes in the bit lines result in an increased unit resistance for the bit line. Bit line driver circuits must be able to provide higher program voltages to overcome the increased voltage drop along bit lines as a result of the increased resistance. The higher program voltages can result in disturb conditions of memory cells that are couple to the bit line.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device with improved data driver circuitry.
SUMMARY OF THE INVENTION
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a memory device comprises an array of non-volatile memory cells arranged in rows and columns, a bit line coupled to a portion of the nonvolatile memory cells, and first and second driver circuits respectively coupled to first and second end regions of the bit line.
In another embodiment, a flash memory device comprises an array of floating gate non-volatile memory cells arranged in rows and columns, a bit line coupled to a portion of the non-volatile memory cells, first and second driver circuits respectively coupled to first and second end regions of the bit line, and a decoder circuit to selectively activate the first and second driver circuits.
A method of programming a non-volatile memory is provided. The method comprises selecting a first non-volatile memory cell, identifying a bit line coupled to the first non-volatile memory cell, and activating either a first or second bit line driver coupled to the identified bit line.
In yet another embodiment, a non-volatile memory device comprises an array of non-volatile memory cells arranged in rows and columns, a bit line having a resistance of R and coupled to the non-volatile memory cells, and X distributed driver circuits coupled to the bit line. A resistance between each of the non-volatile memory cells and any of the driver circuits is less than R/X, and less than R/2(X−1) in another embodiment. In addition, X is two or more.
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Lam David
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
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