Method of addressing plasma panel with addresingpulses of...

Details Method of addressing plasma panel with addresingpulses of... Method of addressing plasma panel with addresingpulses of...

2000-10-20

2003-08-05

Saras, Steven (Department: 2675)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S063000, C345S066000

Reexamination Certificate

active

06603449

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for driving a plasma display panel, and more particularly, to a method for driving a three-electrode surface-discharge
FIG. 1
, and
FIG. 3
show an example of a pixel of the panel shown in
FIG. 1
plasma display panel.
2. Description of the Related Art
FIG. 1
shows a structure of a general three-electrode surface-discharge plasma display panel,
FIG. 2
shows an electrode line pattern of the panel shown in
FIG. 1
, and
FIG. 3
show an example of a pixel of the panel shoen in FIG.
1
. Referring to the drawings, address electrode lines A
1
, A
2
, . . . A
m
, dielectric layers
11
and
15
, Y electrode lines Y
1
, Y
2
, . . . Y
n
, X electrode lines X
1
, X
2
, . . . X
n
, phosphors
16
, partition walls
17
and a MgO protective film
12
are provided between front and rear glass substrates
10
and
13
of a general surface-discharge plasma display panel
1
.
The address electrode lines A
1
, A
2
, . . . A
m
are provided on the front surface of the rear glass substrate
13
in a predetermined pattern. The lower dielectric layer
15
covers the entire front surface of the address electrode lines A
1
, A
2
, . . . A
m
. The partition walls
17
are located on the front surface of the lower dielectric layer
15
parallel to the address electrode lines A
1
, A
2
, . . . A
m
. The partition walls
17
define discharge areas of the respective pixels and prevent optical crosstalk among pixels. The phosphor coating
16
are located between partition walls
17
.
The X electrode lines X
1
, X
2
, . . . X
n
and the Y electrode lines Y
1
,. Y
2
, . . . Y
n
are arranged on the rear surface of the front glass substrate
10
so as to be orthogonal to the address electrode lines A
1
, A
2
, . . . A
m
, in a predetermined pattern. The respective intersections define corresponding pixels. The X electrode lines X
1
, X
2
, . . . X
n
and the Y electrode lines Y
1
,. Y
2
, . . . Y
n
each consist of transparent, conductive indium tin oxide (ITO) electrode lines (X
na
and Y
na
of
FIG. 3
) and metal bus electrode lines (X
nb
and Y
nb
of FIG.
3
). The upper dielectric layer
11
entirely coats the rear surface of the X electrode lines X
1
, X
2
, . . . X
n
and the Y electrode lines Y
1
,. Y
2
, . . . Y
n
. The MgO protective film
12
for protecting the panel
1
against strong electrical fields entirely coats the rear surface of the upper dielectric layer
11
. A gas for forming plasma is hermetically sealed in a discharge space
14
.
The above-described plasma display panel is basically driven such that a reset step, an address step and a sustain-discharge step are sequentially performed in a unit subfield. In the reset step, wall charges remaining from the previous subfield are erased and space charges are evenly formed. In the address step, the wall charges are formed in a selected pixel area. Also, in the discharge-display step, light is produced at the pixel at which the wall charges are formed in the address step. In other words, if alternating pulses of a relatively high voltage are applied between the X electrode lines X
1
, X
2
, . . . X
n
and the Y electrode lines Y
1
, Y
2
, . . . Y
n
, a surface discharge occurs at the pixels at which the wall charges are formed. Here, a plasma is formed in the gas in the discharge space
14
and phosphors
16
are excited by ultraviolet rays and emit light.
FIG. 4
shows the structure of a unit display period based on a driving method of a conventional plasma display panel. Here, a unit display period represents a frame in the case of a progressive scanning method, and a field in the case of an interlaced scanning method. The driving method shown in
FIG. 4
is generally referred to as a multiple address overlapping display driving method. According to this driving method, pulses for a display discharge are consistently applied to all X electrode lines (X
1
, X
2
, . . . X
n
of
FIG. 1
) and all Y electrode lines (Y
1
, Y
2
, . . . Y
480
) and pulses for resetting or addressing are applied between the respective pulses for a display discharge. In other words, the reset and address steps are sequentially performed with respect to individual Y electrode lines or groups, within a unit sub-field, and then the display discharge step is performed for the remaining time period. Thus, compared to an address-display separation driving method, the multiple address overlapping display driving method has an enhanced displayed luminance. Here, the address-display separation driving method refers to a method in which, within a unit subfield, reset and address steps are performed for all Y electrode lines Y
1
, Y
2
, . . . Y
480
, during a certain period and a display discharge step is then performed.
Referring to
FIG. 4
, a unit frame is divided into 8 subfields SF
1
, SF
2
, . . . SF
8
for achieving a time-division gray scale display. In each subfield, reset, address and display discharge steps are performed, and the time allocated to each subfield is determined by a display discharge time. For example, in the case of displaying a 256 step scales with by 8-bit video data in the unit of frames, if a unit frame (generally {fraction (1/60)} second) consists of 256 unit times, the first subfield SF
1
, driven by the least significant bit (LSB) video data, has 1 (2
0
) unit time, the second subfield SF
2
2 (2
1
) unit times, the third subfield SF
3
4 (2
2
) unit times, the fourth subfield SF
4
8 (
2
3
) unit times, the fifth subfield SF
5
16 (2
4
) unit times, the sixth subfield SF
6
32 (2
5
) unit times, the seventh subfield SF
7
64 (2
6
) unit times, and the eighth subfield SF
8
, driven by the most significant bit (MSB) video data, 128 (2
6
) unit times. In other words, since the sum of unit times allocated to the respective subfields is 257 unit times, 255 steps can be displayed, 256 steps including one step which is not display-discharged at any subfield.
After the address step is performed and the display discharge step is then performed with respect to the first Y electrode line Y
1
or the first Y electrode line group, e.g., Y
1
, Y
2
, Y
3
and Y
4
, in the first subfield SF
1
, the address step is performed with respect to the first Y electrode line Y
1
or the first Y electrode line group, e.g., Y
1
, Y
2
, Y
3
and Y
4
, in the second subfield SF
2
. This procedure is applied to the subsequent subfields SF
3
, SF
4
, . . . SF
8
in the same manner. For example, the address step is performed and the display discharge step is then performed with respect to the second Y electrode line Y
2
or the second Y electrode line group, e.g., Y
5
, Y
6
, Y
7
and Y
8
, in the seventh subfield SF
7
. Then, in the eighth subfield SF
8
, the address electrode is performed and the display discharge step is then performed with respect to the second Y electrode line Y
2
or the second Y electrode line group, e.g., Y
5
, Y
6
, Y
7
and Y
8
. The time for a unit subfield equals the time for a unit frame. The respective subfields overlap on the basis of the driven Y electrode lines Y
1
, Y
2
, . . . Y
480
, to form a unit frame. Thus, since all subfields SF
1
, SF
2
, . . . SF
8
exist in every timing, time slots for addressing depending on the number of subfields are set between pulses for display discharging, for the purpose of performing the respective address steps.
According to the above-described driving method, conventionally, the widths of scan pulses applied to the address electrode lines selected corresponding to the respective scanned Y electrode lines and the widths of the pulses of the corresponding display data signals have been fixed. However, the times required for wall charges formed on the respective Y electrode lines due to addressing to wait for the pulse for the first display discharge (
2
in the period T
31
or T
41
of
FIG. 5
) are different. As the times become longer, more wall charges formed at the pixels to be displayed are removed. Thus, according to the conventional driving method, it is highly probable that pixels to be displa

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