Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2002-01-22
2003-12-02
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S189090, C365S171000, C365S173000, C365S232000
Reexamination Certificate
active
06657916
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated memory having a memory cell array including memory cells which are connected to word lines and bit lines. The word lines include a first and a second word line which can be connected to a row decoder for activating the word lines. The first word line can be connected to a supply circuit via a controllable first switching device and the second word line can be connected to the supply circuit via a controllable second switching device for the purpose of reading from or writing to one of the memory cells.
An integrated memory such as, for example, a so-called DRAM (Dynamic Random Access Memory) or MRAM (Magnetoresistive Random Access Memory) generally has a memory cell array which includes bit lines and word lines. In this case, the memory cells are provided at crossover points of the bit lines and word lines. The memory cells are connected to one of the bit lines and one of the word lines. In order to select one of the memory cells, the corresponding word line is activated through the use of a row decoder, as a result of which a data signal of the selected memory cell can subsequently be read out or written via the corresponding bit line.
In order to activate the word lines as rapidly as possible, they are generally constructed in two layers. In this case, each word line has first conductive structures and second conductive structures provided in respectively different wiring planes of the memory. The two different wiring planes are formed by conductive layers of the memory which are provided one above the other or one below the other. In this case, the first conductive structures are usually realized by a metal and the second conductive structures by polysilicon. While the first conductive structures are essentially embodied in an integral manner, the second conductive structures are subdivided into a plurality of segments which are isolated from one another by interruptions. Each of these segments is connected to the associated first conductive structure via a corresponding through-contact. In this case, the second conductive structures are connected to the memory cells.
During the operation of such a memory with segmented word lines, it is not necessary and desirable to drive a word line over its entire length, since this is generally associated with a relatively high power consumption and comparatively slow switching operations. In order to avoid these disadvantages, local driver stages are provided for addressing memory cells, which driver stages, in a manner dependent on an activation state of the word line or the first conductive structures thereof and in a manner dependent on an address, only connect the word line in a segment or the second conductive structures thereof to a supply circuit in the form of a voltage source or current source.
The memory concept described requires at least two wiring planes to be provided, one of which is formed by the metal plane with the integral first conductive structures. Through the latter, the local second conductive structures are connected to the respective voltage source or current source through the use of the driver stages.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory which overcomes the above-mentioned disadvantages of the heretofore-known integrated memory devices of this general type and in which a small number of required wiring planes is made possible for the word lines.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, including:
a memory cell array having word lines including a first word line and a second word line, bit lines, and memory cells connected to the word lines and the bit lines;
a row decoder for activating the word lines, the first word line and the second word line being connectable to the row decoder;
a supply circuit;
a controllable first switching device, the first word line being connectable to the supply circuit via the controllable first switching device for one of reading from and writing to one of the memory cells;
a controllable second switching device, the second word line being connectable to the supply circuit via the controllable second switching device for one of reading from and writing to one of the memory cells; and
a control circuit connected to the first word line, the second word line, the controllable first switching device, and the controllable second switching device, the control circuit driving the controllable first switching device in dependence of an activation state of the second word line and driving the controllable second switching device in dependence of an activation state of the first word line.
Thus, the object of the invention is achieved through the use of an integrated memory which has a control circuit which is connected to the first and second word lines and to the first and second switching devices, in which the control circuit can drive the first switching device in a manner dependent on an activation state of the second word line and the second switching device in a manner dependent on an activation state of the first word line.
In the memory according to the invention, the switching devices of, for example, a driver circuit through the use of which the word lines are connected to a supply circuit for the purpose of reading from or writing to one of the memory cells are not controlled via an additional line in an additional metal plane, rather existing word lines are used for this purpose. Since, for a memory cell access, generally only one word line in each case is used for reading from or writing to memory cells, the other word lines can be used for a control function at this point in time. In this case, it must be ensured through the choice of activation state that when a word line is used as a control line, the content of the memory cells of this word line is not altered. This is generally achieved by the relevant word line having a different state suitable for this when it is used as a control line. By way of example, if the first word line is intended to be connected to the supply circuit for a write access, to that end the second word line is correspondingly activated by the row decoder. The first word line is correspondingly activated for the other case, in which a memory cell access is intended to be carried out via the second word line. If the memory is subdivided into a plurality of word line segments, then the concept according to the invention can be employed for each segment. Fast addressing of the respective memory cells and a low power consumption are made possible as a result.
In such an embodiment of the memory, the memory cell array has at least two word line segments, the first word line segment containing the first and second word lines and a second word line segment containing a third and fourth word line. The first and third word lines and also the second and fourth word lines are connected to one another by driver circuits. The third word line can be connected to the supply circuit via a controllable third switching device and the fourth word line can be connected to the supply circuit via a controllable fourth switching device. Each of the word line segments is assigned a control circuit which is connected to the respective word lines of the respective word line segment and the associated switching device.
According to another embodiment of the integrated memory according to the invention, the driver circuits can in each case be connected to a terminal for an address signal for activating the respective driver circuit. As a result, each word line segment can be selected through the use of a corresponding address signal. For an identical purpose, in a further embodiment, the control circuit can be connected to a terminal for an address signal for activating the control circuit.
According to another feature of the invention, an address terminal for providing an address signal is provided, and the control circuit is connectable to
Hönigschmid Heinz
Kandolf Helmut
Lammers Stefan
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nelms David
Stemer Werner H.
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