Nonvolatile semiconductor memory device having electrically...

Details Nonvolatile semiconductor memory device having electrically... Nonvolatile semiconductor memory device having electrically...

2002-10-07

2003-09-09

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189090, C365S185230

Reexamination Certificate

active

06618288

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a flash memory, i.e., a nonvolatile semiconductor memory device having electrically and collectively erasable characteristics.
2. Description of the Related Art
Recently, in accordance with popularization of computers, word processors, and the like, a plurality of semiconductor memory devices, typically non-volatile semiconductor memory devices, e.g., flash memory, used in such information processors, have been developed and produced.
The flash memory, which is one kind of non-volatile semiconductor memory device, can be made programmable by the user. Further, the flash memory can be rewritten by electrically and collectively erasing the stored data, and then by programming. Therefore, the flash memories have attracted considerable attention as a replacement for magnetic storage devices because they are suitable for integration. Note, there is a necessity of improving redundant circuits, write circuits, and overerasing preventive measures for such a flash memory.
SUMMARY OF THE INVENTION
An object of a first aspect of the present invention is to provide a semiconductor memory device for realizing effective word line redundancy and stable write and verify operations in a semiconductor memory device, to improve the yield and performance of the semiconductor memory device.
An object of a second aspect of the present invention is to provide a semiconductor memory device for reducing the size of the semiconductor memory device, to improve the yield of large capacity semiconductor memories and reduce the cost thereof.
An object of a third aspect of the present invention is to provide a semiconductor memory device for carrying out a delivery test of a semiconductor memory device with “n” rewrite operations at the maximum, and taking into account deterioration due to an increase in the number of rewrite operations, to guarantee the maximum rewrite operations N (N>n) for a user.
An object of a fourth aspect of the present invention is to provide a semiconductor memory device that is capable of supplying a write drain voltage that is not influenced by the threshold voltage of a write voltage supply transistor, thereby correctly writing data to a memory cell even with a low write voltage.
An object of a fifth aspect of the present invention is to provide a semiconductor memory device that correctly reads data even if there is an overerased cell transistor.
An object of a sixth aspect of the present invention is to provide a semiconductor memory device that correctly reads data by saving overerased cell transistors.
An object of a seventh aspect of the present invention is to provide a semiconductor memory device capable of simultaneously erasing a plurality of blocks of memory cells and easily verifying the erased blocks.
An object of an eighth aspect of the present invention is to provide a semiconductor memory device employing two power sources that are easy to use and operable like a single power source.
An object of a ninth aspect of the semiconductior memory device of the present invention is to provide an inexpensive decoder circuit that solves the problems of the prior art. The decoder circuit of the present invention is simple and compact to achieve the full selection and nonselection of word or bit lines in a test mode. This decoder circuit is suitable for high integration.
According to a first aspect of the present invention, there is provided a semiconductor memory device comprising 2
n
word lines, a plurality of bit lines, a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of the word lines and the bit lines, and a threshold voltage of the MIS transistor being externally electrically controllable, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, a sense amplifier for reading data out of the memory cells, a first unit for simultaneously selecting a block of 2
m
(n>m) word lines among the 2
n
word lines, and a second unit for not selecting a block of 2
k
(m>k) word lines among the 2
m
word lines, the second unit not selecting the block of 2
k
word lines and selecting a block of 2
k
word lines prepared outside the 2
n
word lines when any one of the 2
k
word lines among the 2
m
word lines is defective.
The selected word lines may receive a negative voltage, and the unselected word lines receive a zero or positive voltage. The block of 2
n
word lines may form a real cell block, the block of 2
m
word lines may form an erase block, and the block of 2
k
word lines outside the block of 2
n
word lines may form a redundant cell block.
Further, according to a first aspect of the present invention, there is provided a semiconductor memory device comprising 2
n
word lines, a plurality of bit lines, a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of the word lines and the bit lines, and a threshold voltage of the MIS transistor being externally electrically controllable, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, a sense amplifier for reading data out of the memory cells, a first unit for simultaneously selecting a block of 2
m
(n>m) word lines among the 2
n
word lines, and a second unit for not selecting a block of 2
k
(m>k) word lines among the 2
m
word lines, data being written to any memory cell transistor, which is contained in the 2
k
word lines and whose threshold voltage is lower than the potential of an unselected word line, so that the threshold voltage of the memory cell transistor exceeds the potential of the unselected word line, and a block of 2
k
word lines prepared outside the 2
n
word lines being used as redundant word lines.
Further, according to a first aspect of the present invention, there is also provided a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of the word lines and the bit lines, and a threshold voltage of the MIS transistor being externally electrically controllable, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells, wherein each word line is controlled such that a drain current of a memory cell transistor connected to the word line is lower than a channel current thereof, when writing data to the cell transistor to increase the threshold voltage of the memory cell transistor to be higher than the potential of an unselected word line.
Each word line may be controlled by applying a signal in accordance with a pulse signal.
Furthermore, according to a first aspect of the present invention, there is also provided a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of the word lines and the bit lines, and a threshold voltage of the MIS transistor being externally electrically controllable, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells, wherein an output current of the sense amplifier is changed according to a combination of ON states of two load transistors having different capacities, to realize a normal data read operation, an erase verify operation, and a write verify operation.
A reference voltage may be increased to provide a word line with a voltage, which is used to carry out the write verify or erase verify operations on any cell transistor connected to the word line. P-channel type and n-channel type transistors fabricated in the sam

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