Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2000-06-22
2003-08-05
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S088000, C345S089000, C345S095000, C345S100000
Reexamination Certificate
active
06603466
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device composed of a plurality of semiconductor processing sections connected in cascade, and also relates to a display device module using the semiconductor device.
BACKGROUND OF THE INVENTION
FIG. 20
illustrates the system structure of semiconductor processing sections in a conventional liquid crystal display device module. As shown in
FIG. 20
, a plurality of source drivers
51
and gate drivers
52
made of LSIs (large scale integrated circuits) are mounted as source drivers S and gate drivers G, respectively, on a liquid crystal panel
54
in such a state in which they are incorporated in TCPS (tape carrier packages). These source drivers S drive source buslines (not shown) in the liquid crystal panel
54
, while the gate drivers G drive gate buslines (not shown) therein.
Terminals (a group of terminals) of each of the source drivers
51
and gate drivers
52
, which are located on the liquid crystal panel
54
side, are electrically connected to a terminal (not shown) formed by an ITO (indium tin oxide) on the liquid crystal panel
54
through the lines in the TCPs
53
. For instance, electrical connection of the terminals is achieved by thermo-compression bonding with an ACF (anisotropic conductive film) therebetween. Moreover, terminals of each of the source drivers
51
and gate drivers
52
, which are located on a flexible substrate
55
side, are electrically connected to the lines on the flexible substrate
55
through the lines in the TCPs
53
by the above-mentioned ACF or soldering.
Therefore, supply of display-use data signals to the source drivers
51
from a controller circuit
56
and supply of various control signals and power (GND, Vcc) to the source drivers
51
and the gate drivers
52
are performed through the lines on the flexible substrate
55
and the lines on the TCPs
53
.
Here, for the source drivers S, a total of eight source drivers, i.e., the first source driver S(
1
) to the eighth source driver S(
8
), are provided. Meanwhile, for the gate drivers G, a total of two gate drivers, i.e., the first gate driver G(
1
) and the second gate driver G(
2
), are provided.
Regarding the first source driver S(
1
) to the eighth source driver S(
8
), eight identical source drivers
51
are connected in cascade to supply the display-use data signals R, G, B, a start pulse input signal SSPI and a clock signal SCK output from the controller circuit
56
.
Besides, regarding the first gate driver G(
1
) and the second gate driver G(
2
), two identical gate drivers
52
are connected in cascade to supply a clock signal GCK and a start pulse input signal GSPI output from the controller circuit
56
.
FIG. 21
is an enlarged view of the structure of the terminals of the controller circuit
56
that output various signals.
The number of pixels in the liquid crystal panel
54
is, for example, 1024 pixels×3 (RGB) [on the source side]×768 pixels [on the gate side]. Therefore, each of the source drivers
51
of the first source driver S(
1
) to the eighth source driver S(
8
) displays
64
gray scales, and drives 128 pixels×3 (RGB).
FIG. 22
shows the structure of the source driver
51
. As illustrated in
FIG. 22
, the source driver
51
includes a shift register circuit
61
, a data latch circuit
62
, a sampling memory circuit
63
, a hold memory circuit
64
, a reference voltage generator circuit
65
, a DA converter circuit
66
, and an output circuit
67
.
The shift register circuit
61
includes, for example, a plurality of latch circuits (not shown) connected in cascade. For the explanation of the operation, assuming that this source driver
51
is referred to as the first source driver (
1
) of the first stage, the shift register circuit
61
shifts (transmits/transfers) the start pulse input signal SSPI, which was synchronized with a horizontal synchronizing signal of the display-use data signals R, G, B, output from the terminal SSPI of the controller circuit
56
and input to the input terminal SSPin of the source driver
51
, by the clock signal SCK which was output from the terminal SCK of the controller circuit
56
and input to the input terminal SCKin of the source driver
51
.
The start pulse input signal SSPI shifted by the shift register circuit
61
is output from the output terminal SSPout of the source driver
51
so that the output of the final stage is output as the start pulse output signal SSPO, and then input as the start pulse input signal SSPI to the input terminal SSPin of the source driver
51
of the second source driver S(
2
) of the next stage. In this manner, the start pulse input signal SSPI is shifted up to the final stage of the shift register circuit
61
of the source driver
51
of the eighth source driver S(
8
) of the eighth stage.
Moreover, the clock signal SCK input to the shift register circuit
61
is also output from the output terminal SCKout of the source driver
51
, input to the input terminal SCKin of the source driver
51
of the second source driver S(
2
) of the next stage, and transferred up to the source driver
51
of the eighth source driver S(
8
).
On the other hand, 6-bit display-use data signals R, G, B output from the terminals R
1
to R
6
, G
1
to G
6
and B
1
to B
6
of the controller circuit
56
are synchronized with the rise of a clock signal/SCK (the inverted signal of the clock signal SCK), serially input to the input terminals R
1
in to R
6
in, G
1
in to G
6
in and B
1
in to B
6
in of the source driver
51
, respectively, temporarily latched by the data latch circuit
62
and then forwarded to the sampling memory circuit
63
.
Furthermore, the display-use data signals R, G, B which were serially input to the input terminals R
1
in to R
6
in, G
1
in to G
6
in and B
1
in to B
6
in of the source driver
51
are output from the output terminals R
1
out to R
6
out, G
1
out to G
6
out and B
1
out to B
6
out of this source driver
51
, respectively, and forwarded to the source driver
51
of the second source driver S(
2
) of the next stage. In the same manner they are successively transferred up to the source driver
51
of the eighth source driver S(
8
).
The sampling memory circuit
63
samples display-use data signals (a total of 18 bits, i.e., 6 bits for each of R, G, B) sent by time division with the output signal of each stage of the shift register circuit
61
, and stores them until a latch signal LS output from the terminal LS of the controller circuit
56
is input to the terminal LS of the source driver
51
.
These display-use data signals are then input to the hold memory circuit
64
where the display-use data signals input from the sampling memory circuit
63
are latched by the latch signal LS upon the input of the display-use data signals corresponding to one horizontal period of the display-use data signals R, G, B, held until the display-use data signals corresponding to the next horizontal period are input to the hold memory circuit
64
from the sampling memory circuit
63
and then output.
The reference voltage generator circuit
65
generates 64 levels voltages used for, for example, gray-scale display by resister division from reference voltages which are output from the terminals Vref
1
to Vref
9
of the controller circuit
56
and input to the terminals Vref
1
to Vref
9
of the source driver
51
.
The DA converter
66
converts each of the 6-bit display-use data signals (digital) R, G, B input from the hold memory circuit
64
into an analog signal, and outputs the resultant signal to the output circuit
67
. The output circuit
67
amplifies 64 levels analog signals, and outputs them to the terminal (not shown) of the liquid crystal panel
54
from the output terminals Xo-
1
to Xo-
128
, Yo-
1
to Yo-
128
and Zo-
1
to Zo-
128
. The output terminals Xo-
1
to Xo-
128
, Yo-
1
to Yo-
128
and Zo-
1
to Zo-
128
correspond to the display-use data signals R, G, B, respectively. Each of the Xo, Yo and Zo includes
128
terminals.
The terminal Vcc and the terminal
Ogawa Yoshinori
Sakaguchi Nobuhisa
Dharia Prabodh
Shalwala Bipin
Sharp Kabushiki Kaisha
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