Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-02-16
2003-08-12
Saras, Steven (Department: 2775)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C349S048000
Reexamination Certificate
active
06606079
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of electronic devices and, more specifically, the present invention relates to integrated circuits.
2. Background Information
There is currently a need in industry for a cost-effective, efficient and practical method for producing large arrays of electronic elements that can provide, produce or detect voltages. One example of such a need is that of displays, where each voltage becomes a subpixel intensity. Flat panel displays (FPDs) have become a multibillion dollar industry and is presently a growing portion of the high-resolution display market, which is itself growing rapidly. Liquid crystal displays (LCDs) dominate the FPD marketplace. One type of FPD is the active matrix LCDs or active matrix displays. Active matrix displays have a substantial worldwide infrastructure and are a proven commercial technology.
Each picture element or pixel of an active matrix LCD contains one or more thin film transistors. The presence of these active elements make it possible to more clearly and precisely control the brightness of each pixel, which dramatically improves the quality of the display. The advantages of active matrix LCDs become more pronounced as the screen sizes and resolutions increase. However, as screen sizes and resolutions increase, the manufacture and production of active matrix LCDs become increasingly difficult because is challenging to produce active matrix LCDs with high yields. For example, if a particular active matrix LCD has an unacceptably large number of defects, such as for example defective transistors or pixels, the entire active matrix LCD is discarded even though a relatively small number of elements are defective compared to the total number of elements on the active matrix LCD.
One concern with the increasing size of large arrays of electronic elements is that as the number of electronic elements in the array increases, the lower the probability that all of elements in the array will work properly. With existing techniques, it is difficult to test any of the elements until the assembly is complete. If there are imperfections in the array, the imperfections must be tolerated. Otherwise, the entire array must be discarded, or special and expensive techniques must be used to repair the imperfections in the array.
Silicon very large scale integration (VLSI) processes may be used to produce an array of electronic elements over a silicon wafer surface. A disadvantage with using these processes is that silicon wafers are conductive, limited in size and are generally not transparent. Furthermore, large areas of processed silicon wafers can be expensive. In particular, displays that valve the light coming through them need to be largely transparent. Single crystal silicon can be bonded to a glass substrate, and then etched to remove most of the area to achieve transparency, but this is intrinsically wasteful in that, for the sake of maximizing light transmission, the majority of the processed material is discarded, and becomes chemical waste. The underutilization of the precious die area wastes resources, causes greater amounts of chemical waste to be generated in the process, and is generally inefficient and expensive.
There are of course countless other examples of arrays of electronic elements that have useful applications. Another example of such an array is a photodiode array to collect solar energy. Large arrays of silicon photodiodes with concentrating lenses have been made by sawing wafers and using pick and place assembly, but thermal dissipation is poor for large elements, and small elements required too much assembly time.
Thus, what is desired are methods and apparatuses for fabricating and testing arrays of electronic elements.
SUMMARY OF THE INVENTION
In one embodiment, methods and apparatuses providing functionally symmetric integrated circuit dice are disclosed. In one embodiment, an integrated circuit die is disclosed that includes a substrate and a plurality of interface pads to couple the integrated circuit die to receptor site of an electronic device. The plurality of interface pads of the integrated circuit die are arranged in the substrate such that the electronic device operates with the integrated circuit die mounted to the receptor site in any one of a plurality of orientations relative to the receptor site.
In another embodiment, methods and apparatuses providing integrated circuits for display pixels are disclosed. In one embodiment, an integrated circuit device is disclosed that includes a first transistor coupled between an input and a first pixel of a display. The first transistor is configured to couple the first pixel to receive an input signal from the input in response to a first select signal. The integrated circuit device also includes a second transistor coupled between the input and the first transistor. The second transistor is configured to couple the first transistor to receive the input signal in response to a second select signal.
In yet another embodiment, methods and apparatuses for testing integrated circuit dice are disclosed. In one embodiment, a method for testing a plurality of integrated circuits is disclosed to include the steps of arranging a plurality of integrated circuits on a wafer. The plurality of integrated circuits includes a first integrated circuit arranged on the wafer adjacent to a second integrated circuit. A first end of a switchable coupling of the first integrated circuit is coupled across the boundary region of the wafer to a first end of a switchable coupling of the second integrated circuit. A switchable coupling is verified between a second end of the switchable coupling of the first integrated circuit and a second end of the switchable coupling of the second integrated circuit across the boundary region of the wafer. The first integrated circuit is then separated from the second integrated circuit by separating the wafer at the boundary region. Additional features and benefits of the present invention will become apparent from the detailed description, figures and claims set forth below.
REFERENCES:
patent: 5349366 (1994-09-01), Yamazaki et al.
patent: 5363118 (1994-11-01), Okumura
patent: 5545291 (1996-08-01), Smith et al.
patent: 5572211 (1996-11-01), Erhart et al.
patent: 5627557 (1997-05-01), Yamaguchi et al.
patent: 5719591 (1998-02-01), Callahan, Jr. et al.
patent: 5764321 (1998-06-01), Koyama et al.
patent: 5783910 (1998-07-01), Casper et al.
Cohn, MB and Kim, CJ: “Self-Assembling Electrical Networks: An Application of Micromachining Technology”,In Transducers '91: 1991 International Conference on Solid-State Sensors and Actuators: Digest of Technical Papers, pp. 490-493, IEEE (1991).
Alien Technology Corporation
Blakely , Sokoloff, Taylor & Zafman LLP
Kumar Srilakshmi K.
Saras Steven
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