Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-12-20
2003-09-02
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S714000, C438S723000, C438S724000, C438S725000
Reexamination Certificate
active
06613686
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of etching a silicon nitride film. The present invention also relates to a method of producing a semiconductor device and, more particularly, to a method that is effective in forming multilayer interconnects in a semiconductor device having copper interconnects.
2. Description of the Related Art
In recent years, in LSI devices that operate at increasingly higher speeds and are packaged at increasingly higher density, not only transistors but also conductive lines (interconnects) are required to be finer and formed at a higher density.
While Al has been used predominantly as the metallic material to form interconnects, there has been a problem of electro-migration (EM) wherein a temperature rise due to the increasing current density through the interconnects and the heat generated from the entire device mobilizes metal atoms in the interconnects layer, thus eventually generating voids in the portion of migration, leading to interconnects breakage. There is also such a problem that a block of grains referred to as “hillock” is formed in a portion where metal atoms are accumulated, which causes a stress in an insulation layer formed on the wiring, eventually causing cracks.
In order to solve these problems, it has been proposed to use alloys made by adding a trace of Si or Cu to Al. However, sufficient effect of this method cannot be achieved when the interconnects become finer and the packaging density increases, and the use of copper interconnects having higher reliability is being studied.
When copper interconnects are used, a process called the damascene method is employed in which copper is deposited in grooves or holes formed in an insulation film, then the surface is smoothed thereby inlaying the copper in the grooves or holes.
The process of forming the copper interconnects by the damascene method will be described below with reference to accompanying drawings.
FIG. 1
is a sectional view showing the process of the damascene method of inlaying copper in via holes formed in an inter-layer insulation film. As shown in FIG.
1
(
a
), a silicon nitride film is formed as an etching stopper film
5
on an under-layer copper interconnects
4
that is formed by embedding via a barrier film
3
in an inter-layer insulation film
2
provided on a semiconductor substrate
1
, then an inter-layer insulation film
6
is formed thereon from silicon oxide or the like. The silicon nitride film also performs a function of preventing the copper interconnects from being oxidized when forming the silicon oxide film thereon. FIG.
1
(
a
) shows the state of a resist
7
being patterned for the purpose of forming grooves or via holes in the inter-layer insulation film
6
where copper is to be inlaid. Then as shown in FIG.
1
(
b
), the inter-layer insulation film
6
is etched using the resist pattern as the mask. The etching may be done under any dry etching conditions that allow sufficiently high etch selectivity over the silicon nitride film that serves as the stopper film. Then as shown in FIG.
1
(
c
), in order to facilitate contact between the inlaid copper and the under-layer copper interconnects
4
, the stopper film
5
exposed at the bottom of the via hole
8
is removed by dry etching using a fluorocarbon gas. This is followed by inlaying of copper in the via holes
8
thus formed, after forming a barrier film
9
to a thickness of about 10 to 100 nm as shown in FIG.
1
(
d
) in order to prevent copper from diffusing into the silicon oxide film. For the material used to form the barrier film
3
and the barrier film
9
, nitrides of metals having high melting points such as TiN, WN and TaN may be preferably used or the nitrides and the metals having high melting points may be used in a laminated structure. Then a thin copper film that serves as a seed is formed by CVD process or electroless plating process, and a thick copper film
10
is formed by electroplating (FIG.
1
(
e
)). Last, the inter-layer insulation film
6
is exposed by polishing and smoothing by a polishing process such as CMP, thereby to form copper plugs
11
as shown in FIG.
1
(
f
). The under-layer copper interconnects
4
can also be formed by forming interconnect grooves in the inter-layer insulation film
2
, forming the barrier film and the copper film and then polishing by CMP.
Such a process has also been proposed that is based on so-called dual damascene method where via holes and interconnect grooves are combined as shown in FIG.
2
. Similarly to that of FIG.
1
(
a
), the resist
7
is applied in a via hole pattern (FIG.
2
(
a
)) thereby to form the via holes
8
similarly to the above (FIG.
2
(
b
)). Then a resist mask pattern
7
′ is formed again for the purpose of forming grooves (FIG.
2
(
c
)), and the resist is used as the mask for etching the inter-layer insulation film
6
to form the interconnect grooves
12
shown in FIG.
2
(
d
). This is followed by the removal of the stopper film
5
similar to that shown in FIG.
1
(
c
) (FIG.
2
(
e
)), formation of the barrier film
9
(FIG.
2
(
f
)), formation of the copper film
10
(FIG.
2
(
g
)) and CMP polishing, thereby to make the dual damascene (DM) structure
13
as shown in FIG.
2
(
h
).
For the etching of the silicon nitride film used as the etching stopper and the like, various methods have been proposed. In Japanese Unexamined Patent Publication No. Hei 8-97194, for example, a method of plasma etching using CF
4
, O
2
and Ar is disclosed. In Japanese Unexamined Patent Publication No. Hei 10-303187, a method of applying the reactive ion etching (RIE) using a fluorocarbon gas selected from CH
2
F
2
, CH
3
F and CHF
3
, and an inert gas such as Ar is disclosed, describing that particularly anisotrpic etching can be achieved with a high etch selectivity over the silicon oxide film and a high etching rate, by introducing the inert gas at a flow rate at least three times that of the fluorocarbon gas and setting the ambient gas pressure in a range from 1.33 to 67 Pa (10 to 500 mTorr), power density in a range from 1.1 to 5.5 W/cm
2
and substrate temperature in a range from 20 to 95° C. Japanese Unexamined Patent Publication No. Hei 11-186224 describes that use of a process gas containing a fluorocarbon gas that has hydrogen bond and Co gas makes it possible to carry out etching of the silicon nitride film with high etch selectivity over silicon oxide film and, particularly, achieve self-alignment etching for removing a silicon nitride film that has a stepped structure.
These examples teach the methods of etching an ordinary silicon nitride film, but do not suggest as to a semiconductor device that has copper interconnects formed below thereof.
In Japanese Unexamined Patent Publication No. Hei 11-220021, such a method is described as copper provided in an under layer is prevented from being sputtered when tapered walls of upper portions of holes are formed, thereby preventing the copper from depositing on the wall surface of the hole and diffusing into the insulation film, by etching the upper portion of the hole to form a tapered surface after forming the insulation film with a silicon nitride film as an etching stopper film on copper interconnects and forming via holes in the insulation film, then etching the stopper film while introducing 15 sccm, 15 sccm and 400 sccm of CF
4
, CHF
3
and Ar, respectively, into a plasma atmosphere with the substrate temperature being set to about 0° C. and the ambient etching gas pressure to about 67 Pa (500 mTorr). This publication also discloses another method of removing the resist and the stopper film at the same time by placing a semiconductor substrate in a chamber of plasma atmosphere that contains oxygen, after forming via holes in an insulation film. With this method, the silicon nitride film used as the stopper film is removed by physical etching by means of Ar that is introduced together with oxygen into the chamber. At this time, it is described, the copper interconnects located below the
NEC Electronics Corporation
Tran Binh X
Utech Benjamin L.
Young & Thompson
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