Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2002-12-16
2003-12-02
Chervinsky, Boris (Department: 2835)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S718000, C361S719000, C361S708000, C257S706000, C165S080200, C165S080300
Reexamination Certificate
active
06657864
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is directed to microelectronics packaging and more particularly to a method and structure for conducting and dissipating heat from an integrated circuit chip for purposes of thermal management of such devices.
In the field of integrated high speed microcircuit packaging, silicon germanium (SiGe) and other chip technologies can frequently exhibit the property of high thermal density. A high thermal density chip application is typically considered to be equal to or greater than 40 W/cm
2
. When the specified operating ambient temperature is 70 degrees Celsius, as in the case of synchronous optical network/asynchronous transfer mode.(SONET/ATM ) applications, conventional thermal solutions are no longer capable of being used. The present invention addresses the design issues related to high thermal density applications in the forming of a practical thermal solution for high speed chip packaging of this area of applications.
Silicon Germanium Bipolar Junction Transistor architecture used in high speed (typically greater than 1 GHz) RF/Optoelectronic applications exhibit a very high power density, typically at least 40 W/cm
2
. With the nominal operating ambient temperature of 70° C., small chip size (typically 6.5 mm
2
or less), and a low number of controlled collapse chip connections (C4's), i.e., the contact point on the top surface metallurgy (TSM) in a substrate, this form of application requires an enhanced thermal solution. The chip input/output (′I/O″) typically consists of the high speed nets on the periphery of the array and the voltages, grounds and controls distributed across the entire C4 array. The chip can be designed for any combination of peripheral and or area array as required by the application.
A thermal solution for high power density applications, where the ambient temperature is approximately 70° C. and the maximum transistor junction temperature is approximately 110° C., is impossible to achieve with normal techniques such as direct lid attach (DLA) and thermally conductive grease with cap and heat sink. These applications employ physically small SiGe chip of typically less than 6.5 mm
2
. Small chips cannot be cooled with standard DLA solutions because they lack the mechanical strength to support a suitable heat sink structure. Chips less than 6,5 mm
2
do not have the mechanical strength at the C4/TSM solder interface to reliably support a DLA thermal solution. The number of C4's on the small chip restricts the heat flow into the substrate or chip carrier and this limits the effectiveness of the thermal flow in that direction.
Accordingly, it is a purpose of the present invention to provide an improved thermal path into the substrate which bypasses the C4's, and which directs the heat into metal vias designed into the substrate and which may also connect into a thermal dissipating metal mesh within the substrate. The mechanical interface between the chip backside and proposed solution is decoupled and the thermal conduction path is enhanced by using a thin gap and thermally conductive grease. The proposed thermal solution provides an enhanced thermal path between the chip and the substrate, and the substrate and the printed circuit board without compromising the reliability of the chip C4 to substrate TSM solder interface.
This thermal solution does not depend on the chip C4's to conduct the chip's dissipated heat to the substrate and second level (substrate to circuit board) attachment. This enables the heat to flow into the second level assembly which effectively doubles the thermal flow away from the chip as compared to a standard thermal solution.
These and other purposes of the present invention will become more apparent after referring to the following description considered in conjunction with the accompanying drawings.
BRIEF SUMMARY OF THE INVENTION
The purposes of the present invention have been achieved by providing a high power density thermal packaging structure comprising:
a printed circuit board having a plurality of top surface connection pads and horizontal metal planes within the printed circuit board connected to the plurality of top surface connection pads;
a ceramic substrate having a first plurality of vertical vias which electrically connect the ceramic substrate top surface and bottom surface, the ceramic substrate attached to the printed circuit board top surface with a first solder connection, this first solder connection is typically a solder ball grid array or solder column grid array;
an integrated circuit chip having a plurality of bottom surface connection pads, the integrated circuit chip attached to the ceramic substrate top surface with a second solder connection between the first plurality of vertical vias and the plurality of integrated circuit chip bottom surface connection pads, this second solder connection is typically a C4 solder connection;
a second plurality of vertical vias arrayed on the perimeter of the ceramic substrate and connecting the ceramic substrate top surface and bottom surface, the second plurality of vertical vias also attached to the printed circuit board top surface with the first solder connection between the second plurality of vertical vias and the plurality of printed circuit board top surface connection pads;
a first layer of a thermally conductive elastomer on the integrated circuit chip top surface;
a second layer of a thermally conductive elastomer on a perimeter portion of the ceramic substrate top surface; and
a lid having a top surface and a perimeter bottom surface and a recess portion, the recess portion in contact with the first layer of a thermally conductive elastomer and the perimeter bottom surface in contact with the second layer of a thermally conductive elastomer and in thermal contact with the second plurality of vertical vias and attached to the ceramic substrate top surface.
The high power density thermal packaging structure may further comprise:
horizontal metal planes within the ceramic substrate connected to the second plurality of vias;
a third layer of a thermally conductive elastomer on the lid top surface; and
a heat sink in contact with the third layer of thermally conductive elastomer and attached to the lid top surface thereby providing a thermally conductive interface between the lid and the heat sink.
The present invention also discloses a method for providing a high power density thermal packaging solution comprising the steps of:
providing a printed circuit board having a plurality of top surface connection pads and horizontal metal planes within the printed circuit board connected to the plurality of top surface connection pads;
providing a ceramic substrate having a first plurality of vertical vias which electrically connect the ceramic substrate top surface and bottom surface, a second plurality of vertical vias arrayed on the perimeter of the ceramic substrate and connecting the ceramic substrate top and bottom surface, and horizontal metal planes within the ceramic substrate connected to the second plurality of vias;
providing an integrated circuit chip having a plurality of bottom surface connection pads;
applying a first layer of a thermally conductive elastomer on the integrated circuit chip top surface;
applying a second layer of a thermally conductive elastomer on a perimeter portion of the ceramic substrate top surface;
attaching the integrated circuit chip to the ceramic substrate top surface with a solder connection between the first plurality of vertical vias and the plurality of integrated circuit chip bottom surface connection pads;
providing a lid having a top surface and a perimeter bottom surface and a recess portion;
attaching the lid to the integrated circuit chip top surface so that the recess portion is in contact with the first layer of thermally conductive elastomer and attaching the perimeter bottom surface portion to the ceramic substrate so that the bottom surface portion is in contact with the second layer of thermally conductive elastomer; and
Dyckman Warren D.
Pillai Edward R.
Zitz Jeffrey A.
Chervinsky Boris
Cioffi James J.
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