Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-03-01
2003-09-02
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185030
Reexamination Certificate
active
06614686
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a non-volatile memory circuit constituted by cell transistors which have a non-conductive trapping gate and which are capable of storing multiple bit data, and, more particularly, to a non-volatile memory circuit which has a cell array constitution capable of simultaneously reading out stored data from a multiplicity of cell transistors.
TECHNICAL BACKGROUND
Non-volatile memories that utilize semiconductors are widely used as information recording media because such non-volatile memories are capable of holding information even if the power supply is OFF, and of high speed read-out. In recent years, non-volatile memories have been utilized in mobile information terminals, and utilized as recording media for digital cameras and for digital music in the form of MP3 data, for example.
Non-volatile memories, such as the flash memories that are currently in widespread use, are constructed having, on a channel region between a source region and drain region, a conductive floating gate and a control gate. A non-volatile memory of this kind is constituted such that a floating gate is buried in a gate insulating film, and one-bit information is stored according to whether charge is or is not injected into this floating gate. Due to the fact that the floating gate of such widely used non-volatile memories is conductive, when defects, however small, are present in the gate oxide film, electrons in the floating gate are all lost via these defects and there is a problem in that high reliability is unattainable.
Other than the widely used non-volatile memories mentioned above, a new type of non-volatile memory has been proposed that is provided with a non-conductive charge trapping gate in place of a floating gate, and that stores two-bit information by causing charge to be trapped locally at the source side and the drain side of the trapping gate. For example, a non-volatile memory of this kind is disclosed in the PCT application WO99/07000 “Two Bit Non-Volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping”. Since the trapping gate of this non-volatile memory is non-conductive, the probability of electrons injected locally being lost is low, and it is thus possible to make reliability high.
FIG. 1
is a figure to show the constitution of a cell transistor of the above-mentioned conventional two-bit non-volatile memory. (
1
) of
FIG. 1
is a cross-sectional view thereof, and (
2
) of
FIG. 1
is an equivalent circuit diagram thereof. Source-drain regions SD
1
, SD
2
are formed at the surface of a silicon substrate
1
, and a trapping gate TG formed from a silicon nitride film or the like, and a control gate CG of a conductive material, are formed on a channel region. The trapping gate TG is buried in an insulating film
2
made of silicon oxide film or the like such that the whole body is a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure. By utilizing the difference in the bandgaps of the silicon nitride film and the silicon oxide film, it is possible to cause charge to be trapped and held in the silicon nitride film.
One feature of the non-volatile memory is that the trapping gate TG is constituted from a non-conductive substance such as an insulating body, or a dielectric body, and, in a case in which charge is injected into this trapping gate TG, charge within the trapping gate is unable to move. As a result, it is possible to make a distinction between a case in which charge is injected in the vicinity of a first source-drain region SD
1
, and a case in which charge is injected in the vicinity of a second source-drain region SD
2
, and it is thus possible to record two-bit data.
(
2
) of
FIG. 1
is an equivalent circuit diagram of the above-mentioned two-bit non-volatile memory. Since the trapping gate TG is non-conductive, this trapping gate TG is equivalent to a constitution in which separate MOS transistors are respectively formed in a first trapping gate region TSD
1
in the vicinity of the first source-drain region SD
1
, and in a second trapping gate region TSD
2
in the vicinity of the second source-drain region SD
2
. Further, in the course of the above-described read-out and programming (write) operations, the first and second source-drain regions SD
1
, SD
2
are utilized either as source regions or drain regions, and these source or drain regions SD
1
, SD
2
are therefore referred to, in this specification, as the first source-drain region SD
1
and the second source-drain region SD
2
, respectively.
FIG. 2
is a figure to illustrate programming, erasure and read-out of a conventional two-bit non-volatile memory. The voltage applied to the first source-drain region SD
1
is termed V(SD
1
), the voltage applied to the second source-drain region SD
2
is termed V(SD
2
), and the voltage applied to the control gate CG is termed Vg.
As shown in (
1
) of
FIG. 2
, the programming (write) of the non-volatile storage memory is executed by applying voltages Vg=10V, V(SD
1
)=0V, V(SD
2
)=6V, for example, and by thus injecting hot electrons produced in the vicinity of the second source-drain region SD
2
into the second trapping gate region TSD
2
close to the second source-drain region SD
2
.
In addition, in the course of an erase operation, as shown in (
2
)
FIG. 2
, Vg=−5V is applied to the control gate CG, and 5V is applied to the first or second source-drain region SD
1
or SD
2
, or to both of them, to extract electrons from the trapping gate TG by utilizing the FN tunnel effect (the Fowler-Nordheim Tunnel effect). As a result of injection, at the same time, of hot holes produced in the vicinity of the source-drain regions SD
1
, SD
2
, into the trapping gate TG, the charge is neutralized within the trapping gate TG.
Next, with regard to read-out, a voltage, whose bias is the reverse of the voltage of the programming operation, is applied between the first and second source-drain regions SD
1
, SD
2
, to detect whether or not electrons are trapped in the second trapping gate region TSD
2
. In other words, in order to read out the state of the second trapping gate region TSD
2
, voltages applied are Vg=3V, V(SD
1
)=1.6V, V(SD
2
)=0V, for example. Here, as shown in (
3
) of
FIG. 2
, when electrons are present in the second trapping gate region TSD
2
in the vicinity of the second source-drain region SD
2
, the channel below the gate does not extend so as to touch the second source-drain region SD
2
, and, consequently, a channel current does not flow (0 data storage state). Conversely, as shown in (
4
) of
FIG. 2
, when electrons are not present in the second trapping gate region TSD
2
in the vicinity of the second source-drain region SD
2
, the channel reaches as far as the second source-drain region SD
2
, and, consequently, a channel current flows (1 data storage state). It is thus possible to detect whether or not electrons have accumulated in the second trapping gate region TSD
2
, and to detect the ON and OFF of a cell transistor, that is, the existence of a current.
Furthermore, in read-out of the non-volatile storage memory, when, as shown in (
5
) of
FIG. 2
, voltages applied are: Vg=3V, V(SD
1
)=0V, V(SD
2
)=1.6V, i.e. when the voltage application state between the first and second source-drain regions is the reverse of that in (
3
) of
FIG. 2
mentioned above, even if electrons are, for example, present in the second trapping gate region TSD
2
, the state is the same as a MOS transistor whose channel is pinched off, and, as a result of an expanding depletion layer between the second source-drain region and the substrate, a channel current flows. Therefore, in a voltage application state of this kind, it is possible to detect whether or not electrons have accumulated in the first trapping gate region TSD
1
in the vicinity of the first source-drain region SD
1
, irrespective of the existence of electrons in the second trapping gate region TSD
2
.
As described above, a con
Arent Fox Kinter Plotkin & Kahn PLLC
Fujitsu Limited
Hoang Huan
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