Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1999-01-07
2003-06-17
Talbott, David L. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S254000, C174S259000
Reexamination Certificate
active
06580035
ABSTRACT:
The present invention relates to an electronic device and, in particular, to a flexible adhesive membrane and to an electronic device employing same.
There are many conventional ways of depositing solder or conductive adhesives for the bonding of electronic components and flip chip semiconductor devices to substrates, such as those set forth, for example in U.S. Pat. No. 3,401,126 entitled “Method of Rendering Noble Metal Conductive Composition Non-Wettable by Solder”, U.S. Pat. No. 3,429,040 entitled “Method of Joining a Component to a Substrate”, U.S. Pat. No. 4,113,981 entitled “Electrically Conductive Adhesive Connecting Arrays of Conductors”, U.S. Pat. No. 5,074,947 entitled “Flip-Chip Technology Using Electrically Conductive Polymers and Dielectrics”, U.S. Pat. No. 5,196,371 entitled “Flip Chip Bonding Method Using Electrically Conductive Polymer Bumps”, U.S. Pat. No. 5,237,130 entitled “Flip Chip Technology Using Electrically Conductive Polymers and Dielectrics”, and U.S. Pat. No. 5,611,140 entitled “Method of Forming Electrically Conductive Polymer Interconnects on electrical Substrates”. One problem common to these prior art techniques is that they all require operations that are substantially different from those normally associated with semiconductor fabrication. As a result, a substantially different kind of operation and process is being employed and a new business has evolved in which service companies perform solder deposition onto semiconductor wafers as well as adhesive deposition onto such wafers.
With the advancing usage of multi-chip module (MCM) packaging, knowledge of whether each individual semiconductor die is operative under the anticipated functional and stress conditions should be obtained before assembly of such dies into the MCM, so as to increase the yield of operative MCMs and to lower the cost thereof. This so-called known-good-die (KGD) testing is especially important for the large-volume production, such as is the case in the personal computer industry where many complex microprocessors, cache and other memory chips, and other electronic components, are assembled onto a large computer motherboard.
Conventionally, the stressing of semiconductor die (for burn in and electrical testing) is normally performed on an individual semiconductor die mounted in an individual test socket or carrier. The cost and time involved are substantial (see, Carter et al. “Known Good Die Comes of Age”,
Semiconductor International
, October 1997). Besides the semiconductor die manufacturers, there are many companies now performing services as die processors. The cost of such processing could be reduced if die testing and stressing could be performed at the semiconductor wafer level. However, a suitable interface is required between the wafer and the test probes and other test equipment executing the testing protocol and under the test temperature environmental conditions.
This separation of these deposition, testing and other processing operations from the semiconductor wafer fabrication operations creates a time delay, perhaps as long as one to four weeks, in overall processing. This delay is unacceptable, especially where a problem arises because the delay in communicating the problem to the semiconductor wafer manufacturer delays the making of any required process change or improvement and usually results in wafers that are processed in the interim being unusable, further reducing the yield of acceptable product and increasing its cost.
Thus, there is a need for a fast and easy method of forming membranes of conductive adhesive and insulating adhesive underfill for attachment to electronic components, such as semiconductor flip chips, whether for the purpose of flip chip probing and stress testing, or for subsequent bonding to a substrate, or both.
In the case of solder deposition, solderable metallization must be first deposited on the contacts or bond pads which are usually aluminum, such as by an electroless, electrolytic, or vacuum evaporation process, so that the solder paste may be stenciled onto the solderable contacts or bond pads and reflowed to form solder bumps that will adhere to the contacts or bond pads. In the case of conductive adhesive, the contacts or bond pads are normally passivated with precious metal to prevent oxidation before the conductive adhesive in paste form is deposited, such as by screening or stenciling, onto the contacts or bond pads. The lowest cost for these processes is estimated to be about US$50 for a 6-inch diameter semiconductor wafer, even for high-volume production. While precious metal passivation must always be first made before any use of the conductive adhesive, the flash process for depositing nickel-gold or nickel-palladium combinations of layers is well established and can readily be accommodated in a sequential fabrication operation within almost any semiconductor fabrication facility.
Semiconductor die and other flip-chip components normally have fine contact pad size and pitch (i.e. center-to-center separation between adjacent contact pads or other features), whereas the substrate or “next-level board” to which they are bonded often employ lower-cost substrate materials such as FR4, ceramic, and other organic laminates, which in general afford electrical interconnections and contact pads that are normally on a larger scale and pitch than those afforded in semiconductor processing. For example, present-day semiconductor processing can produce micron-size and submicron-size features while the state-of-the-art etching techniques for FR4/copper and thick-film deposition on ceramic or organic substrates can produce features of about 75 microns or larger size. Thus, there is a need for making reliable and low cost interconnections without sacrificing the fine-feature size and fine pitch capabilities of semiconductor processing to accommodate lesser capabilities of the substrate processing operation.
Another consideration in attaching semiconductor and other flip-chip components to a substrate is that of obtaining and maintaining intimate interfacial contact between the component and the substrate so that there will be adequate thermal energy transfer which leads to lower temperature operation and to greater reliability. Good thermal conductivity will not be obtained where air, voids or other foreign matter is trapped between the chip and the substrate, and is particularly difficult to obtain where a patterned membrane of conductive and insulating organic polymer adhesive is employed. If a non-flowing dielectric underfill material is used, such as an epoxy of the sort described in U.S. Pat. No. 5,074,947 entitled “Flip-Chip Technology Using Electrically Conductive Polymers and Dielectrics” issued to Estes et al. voids will almost always form along the interface and thus, poor thermal conductivity will result across the interface between the electronic component and the substrate. In addition, if a rigid conductive adhesive of the sort described in the Estes et al. patent is used, the conductive adhesive will be subject to delamination and fracture under thermal stress and the interconnections formed thereby will be unreliable; the non-adhering dielectric underfill will not relieve the strain on the conductive adhesive and truly improve the aforementioned poor reliability.
A membrane having a pattern of conductive pads within an insulating matrix employing a high strength adhesive system having a high modulus of elasticity is reported by R. W. Johnson, et. al. “Adhesive Based Flip Chip Technology for Assembly on Polyimide Flex Substrates”,
International Conference on Multichip Modules
, (April, 1997). One problem with the approach reported by Johnson et. al. is that their rigid resin system having a high modulus of elasticity, such as a novolac epoxy base resin having a high glass transition temperature Tg of typically 150° C. and a modulus of elasticity of about 2,000,000 psi, can not accommodate the substantial differences between the coefficients of thermal expansion (CTE) of semiconductor dies or chips and of subs
Amerasia International Technology Inc.
Dann Dorfman Herrell & Skillman P.C.
Norris Jeremy
Talbott David L.
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