Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input
Reexamination Certificate
2002-03-18
2003-06-17
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Phase shift by less than period of input
C327S258000
Reexamination Certificate
active
06580300
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a polyphase signal generator which generates signals spaced in phase 90 degrees apart. In particular, this invention relates to a polyphase signal generator which implements the equivalent function with a small-scale circuit configuration.
BACKGROUND OF THE INVENTION
A conventional four-phase signal generator will be taken as an example of a conventional polyphase signal generator.
FIG. 2
shows a configuration of a conventional four-phase signal generator which is explained in C-12-11, 2001 National Convention Record of the Institute of Electronics, Information and Communication Engineers of Japan.
In
FIG. 2
, reference number
1
denotes a first signal input terminal,
2
denotes a second signal input terminal,
3
denotes a first signal output terminal,
4
denotes a second signal output terminal,
11
denotes a first delay circuit,
12
denotes a second delay circuit,
21
denotes a first phase interpolation circuit,
22
denotes a second phase interpolation circuit,
211
denotes a third signal input terminal,
212
denotes a fourth signal input terminal,
221
denotes a fifth signal input terminal, and
222
denotes a sixth signal input terminal.
Operation of the conventional four-phase signal generator will now be explained. The first delay circuit
11
and the second delay circuit
12
have the same configuration and provide equal phase delays &thgr;. The first phase interpolation circuit
21
and the second phase interpolation circuit
22
have the same configuration and equal internal phase delays &dgr;. A signal phase of the third signal input terminal
211
is denoted by IN
21
a.
A signal phase of the fourth signal input terminal
212
is denoted by IN
21
b.
A signal phase of the fifth signal input terminal
221
is denoted by IN
22
a.
A signal phase of the sixth signal input terminal
222
is denoted by IN
22
b.
An output signal phase of the first signal output terminal
3
is denoted by OUT
0
, and an output signal phase of the second signal output terminal is denoted by OUT
90
.
Signals spaced in phase 180 degrees apart are input to the first signal input terminal
1
and the second signal input terminal
2
. The phase shift of 180 degrees can be obtained easily by inverting a signal. Denoting a signal phase of the first signal input terminal
1
by IN
0
and a signal phase of the second signal input terminal
2
by IN
180
, therefore, the following equations are satisfied as regards signal phases.
INO
=0 (1)
INI
180
=180 (2)
An output of the first delay circuit
11
is connected to both the third signal input terminal
211
and the fourth signal input terminal
212
. As regards the phases, therefore, the following equation is satisfied.
IN
21
a=IN
21
b=IN
0
+&thgr;=&thgr; (3)
An output of the second delay circuit
12
is connected to the fifth signal input terminal
221
. The second signal input terminal
2
is connected to the sixth signal input terminal
222
. Therefore, the following equations are satisfied as regards signal phases.
IN
22
a=IN
0
+2·&thgr;=2·&thgr; (4)
IN
22
b=INI
180
=180 (5)
The first phase interpolation circuit
21
and the second phase interpolation circuit
22
output signals with output phases represented by the following equations in response to two signal input phases.
OUT0
=
δ
+
(
IN21a
+
IN21b
)
/
2
=
δ
+
θ
(
6
)
OUT90
=
δ
+
(
IN22a
+
IN22b
)
/
2
=
δ
+
(
2
·
θ
+
180
)
/
2
=
δ
+
θ
+
90
(
7
)
It will be appreciated from the equations (6) and (7) that the signal phase of the first signal output terminal
3
and the signal phase of the second signal output terminal
4
always maintain the phase difference relation of 90 degrees irrespective of the phase delay &thgr; of the first delay circuit
11
and the second delay circuit
12
and the internal phase delay &dgr; of the first phase interpolation circuit
21
and the second phase interpolation circuit
22
. In other words, even when the phase delays &thgr; and &dgr; are varied by a variation of an environment such as the operation temperature or the power supply voltage, four-phase signals spaced in phase accurately 90 degrees apart can be obtained from the output signal of the first signal output terminal
3
, the output signal of the second signal output terminal
4
, an inverted output signal of the first signal output terminal
3
, and an inverted output signal of the second signal output terminal
4
.
Operation of the phase interpolation circuits will now be explained.
FIG. 3
is a diagram showing an example of a detailed configuration of the first phase interpolation circuit
21
and the second phase interpolation circuit
22
. In
FIG. 3
, reference number
51
denotes a high potential power supply voltage,
52
denotes a low potential power supply voltage,
53
denotes a first positive-phase input terminal,
54
denotes a first negative-phase input terminal,
55
denotes a second positive-phase input terminal,
56
denotes a second negative-phase input terminal,
57
denotes a positive-phase output terminal,
58
denotes a negative-phase output terminal,
59
denotes a first current source,
60
denotes a second current source,
61
-
64
denote NPN transistors, and
65
and
66
denote resistors. The first signal output terminal
3
and the second signal output terminal
4
shown in
FIG. 1
correspond to the positive-phase output terminal
57
and the negative-phase output terminal
58
shown in FIG.
3
.
The first current source
59
and the second current source
60
flow currents of the same current value I
0
. The NPN transistors
61
to
64
have the same characteristic. The resistor
65
and the resistor
66
have the same resistance value R. The first positive-phase input terminal
53
is the third signal input terminal
211
shown in FIG.
2
. The second positive-phase input terminal
55
is the fourth signal input terminal
212
shown in FIG.
2
. Each of the first negative-phase input terminal
54
and the second negative-phase input terminal
56
is supplied with a reference voltage.
Supposing an input signal IN
21
a
of the first positive-phase input terminal
53
and an input signal IN
21
b
of the second positive-phase input terminal
55
to be sine waveforms, t to be time, &phgr;(t) to be a phase at the time t, &xgr; to be a phase difference between IN
21
a
and IN
21
b,
and Vref to be the reference voltage applied to the first negative-phase input terminal
54
and the second negative-phase input terminal
56
, the input signal IN
21
a
and the input signal IN
21
b
can be represented by the following equations.
IN
2
l
a=Vref+
sin &phgr;(
t
) (8)
IN
21
b=Vref+
sin{&phgr;(
t
)+&zgr;}(9)
If each of a differential pair formed of the NPN transistors
61
and
62
and a differential pair formed of the NPN transistors
63
and
64
conducts a linear operation in response to its input signal, it divides a current source current I
0
in proportion to an amplitude of the input signal. Supposing a high potential power supply voltage
51
to be Vcc, therefore, a collector current Ia
1
of the NPN transistor
61
, a collector current Ib
1
of the NPN transistor
63
, and an output voltage V
2
of the negative-phase output terminal
58
can be represented by the following equations.
Ia1
=
(
I0
/
2
)
{
1
+
sin
ϕ
(
t
)
}
(
10
)
Ib1
=
(
I0
/
2
)
[
1
+
sin
{
ϕ
}
(
t
)
+
ζ
]
(
11
)
V2
=
Vcc
-
R
{
Ia1
+
Ia2
}
=
Vcc
-
R
(
I0
/
2
)
[
2
+
sin
ϕ
(
t
)
+
sin
{
ϕ
(
t
)
+
ζ
}
]
=
Vcc
-
R
(
I0
/
2
)
[
2
+
2
×
cos
(
ζ
/
2
)
&
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Tran Toan
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