Optics: measuring and testing – With sample preparation
Reexamination Certificate
2000-07-24
2003-12-02
Font, Frank G. (Department: 2877)
Optics: measuring and testing
With sample preparation
C356S237200, C356S237500
Reexamination Certificate
active
06657707
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for performing metallurgical inspection and analysis of contact pads of semiconductor devices. More particularly, the present invention pertains to a method of sample preparation for performing metallurgical inspection and analysis of contact pads and interfaces in flip-chip semiconductor integrated circuit (IC) devices and assemblies, which method reveals pad surfaces and thus permits inspection and analysis of metallurgical structure, characteristics, and properties which are not otherwise feasible.
BACKGROUND OF THE INVENTION
An increasingly important aspect of semiconductor integrated circuit (IC) manufacturing technology is mounting of the semiconductor IC chip or die to an appropriate substrate. Frequently, this requires providing the chip or die with as many input/output (“I/O”) terminals as is possible. As a consequence of the requirement for a large number of terminals to be formed on al limited amount of chip or die surfacer, so-called “flip-chip” structures and bonding techniques have been developed in order to provide high areal density interconnections between the IC chip or die and the substrate.
According to flip-chip methodology, the IC chip or die is mounted via direct bonding to the substrate. Generally, the flip-chip process entails disposing a plurality of solder balls or bumps on the upper major surface of the chip or die, “flipping ” the chip or die over so that the solder balls or bumps face the substrate, mating them with corresponding bonding pads located on the substrate, and then heating the chip or die and the substrate to effect reflow of the solder bumps. Once reflowed, each solder ball or bump forms a bond between the chip or die and the corresponding bonding pad on the substrate, which bonded combination functions as both an electrical and physical contact.
A variant of the above-described flip-chip bonding technology, known as “controlled collapse chip connection” or “C4”, is particularly useful in applications having a very high density of electrical interconnections. According to C4 methodology, electrically conductive balls or bumps comprising a solder material (i.e., alloy) are formed on the IC chip or die as well as on the mating surface of the substrate. Bonding between the two sets of solder balls or bumps is effected by application of heat and mechanical pressure to the chip or die and the substrate. The application of heat causes both sets of solder-based balls or bumps to reflow, thereby providing physical and ohmic connection therebetween, while the applied mechanical pressure causes the solder-based balls or bumps to at least partially collapse, creating a “pancake” shape which advantageously reduces interconnection length and resistance.
According to conventional manufacturing practices, e.g., with silicon (Si)-based semiconductor wafers, the solder-based balls or bumps are typically comprised of a lead (Pb)-based solder, e.g., a lead-tin (Pb—Sn) alloy such as of 97% Pb and 3% Sn (by weight), and are formed, as by use of vacuum or electrodeposition techniques, on electrically conductive contact pads comprising a multi-layer stack of metals, alloys, and phased-composition metal combinations. Referring to
FIG. 1
, schematically shown therein in cross-section is an example of a C4—type solder ball or bump formed on an underlying multi-layer contact pad. It should be recognized, however, that the various features and layers shown in the figure are not drawn to scale but are represented therein as to best illustrate the pertinent features thereof.
As shown in
FIG. 1
, C4—type solder ball or bump
8
is disposed over a major surface S of a semiconductor wafer
1
(or chip or die thereof), e.g., of silicon (Si). The ball or bump
8
may range in diameter from about 100 to about 200 &mgr;m and is preferably composed of the above-mentioned 97% Pb 3% Sn alloy. Intermediate the ball or bump
8
and wafer or chip surface S is an electrically conductive contact pad CP of multi-layer structure, comprised of at least four (4) vertically stacked layers, each of which is chosen for providing good mutual adhesion. The various component layers may be deposited by conventional techniques, such as sputtering, vacuum evaporation, CVD, etc. Contact pad CP includes, in overlying sequence from wafer or chip surface S: a series of layers, including adhesion and transition layers, e.g., an aluminum (Al) or Al-based layer
2
; a chromium (Cr) or Cr-based layer adhesion
4
; a chromium-copper (Cr—Cu) phased (i.e., heterogeneous) transition layer
6
; and a copper (Cu) or Cu-based layer
7
for facilitating wetting by the Pb-based solder ball or bump
8
formed on the upper surface
7
U thereof. In addition to these layers, a thin gold (Au) or Au-based layer may, if desired, be formed over Cu or Cu-based layer
7
for increasing corrosion/oxidation resistance of the contact.
Flip-chip contact arrangements, such as described above, are susceptible to exhibiting poor ohmic contact performance, or even failure, via several different mechanisms, including, inter alia, void formation, electromigration, intermetallic diffusion, adhesion loss, etc., necessitating performing a failure analysis and/or inspection with the aim of determining the particular mechanism responsible for the poor ohmic contact performance or failure. However, methodology for performing rapid, simple sample preparation for failure analysis and/or inspection of the various layers and interfaces constituting the flip-chip physical and electrical contact, is presently unavailable. Moreover, methodology which reveals all of the pertinent structure for enabling study and analysis of the metallurgy/microstructure of the various layers, alloys, interfaces, and intermetallics of flip-chip devices is considered of paramount significance in developing diagnostic procedures having as their aim the development of flip-chip electrical contacts having increased reliability and improved ohmic resistance characteristics.
Accordingly, there exists a need for improved methodology for reliable, rapid, and simple sample preparation for performing metallurgical analysis and/or inspection of electrical contact layers, surfaces, and interfaces between layers underlying solder bumps or balls in IC flip-chip devices, which methodology is capable of revealing all pertinent metallurgical and/or microstructural features of flip-chip contacts and does not require specialized, costly equipment or apparatus.
The present invention, wherein at least one solder bump or ball forming part of a contact arrangement of IC flip-chip device is selectively removed, as by a room temperature chemical etching process, to reveal the surface of the underlying multi-layer contact pad and render it and its various component layers and interfaces therebetween accessible to a variety a metallurgical, microstructural, and other type analytical and inspection tests and procedures, effectively addresses the need for improved methodology for development of reliable, adherent, low ohmic resistance flip-chip contacts and devices. Further, the means and methodology provided by the present invention enjoy diverse utility in the manufacture of numerous types of electrical and electronic devices provided with raised contacts.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is an improved method for simple, reliable, and rapid sample preparation of flip-chip devices for metallurgical analysis and/or testing of electrical contact layers, surfaces, and interfaces.
Another advantage of the present invention is an improved method for performing metallurgical analysis and/or inspection of electrical contact layers, surfaces, and interfaces underlying solder balls or bumps of electrical or electronic devices.
Yet another advantage of the present invention is an improved method of performing metallurgical analysis and/or inspection of electrical contact pad layers, surfaces, and interfaces underlying Pb-based solder bumps or balls of a flip-chip semiconductor IC device.
Addition
Master Raj
Morken David Bruce
Advanced Micro Devices , Inc.
Font Frank G.
Punnoose Roy M.
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