Semiconductor device manufacturing: process – Including control responsive to sensed condition – Optical characteristic sensed
Reexamination Certificate
2002-03-13
2003-04-29
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Optical characteristic sensed
C438S706000, C438S714000
Reexamination Certificate
active
06555396
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally pertains to semiconductor processing, and, more particularly, to forming vias through process layers formed above a semiconducting substrate.
2. Description of the Related Art
The manufacture of semiconductor devices generally involves the formation of various process layers, selective removal or patterning of portions of those layers, and deposition of yet additional process layers above the surface of a semiconducting substrate. The substrate and the deposited layers are collectively called a “wafer.” This process continues until a semiconductor device is completely constructed. The process layers may include by way of example insulation layers, gate oxide layers, conducting layers, layers of metal or glass, etc.
A significant portion of this process involves the formation of holes or vias through one or more of the process layers to a surface of an underlying process layer. As shown in
FIG. 1
, these vias
10
are typically formed by placing a mask layer
12
over a surface
13
of a partially formed semicondutor device
14
. An open region
16
in the mask layer
12
leaves at least a portion of a layer
18
exposed. The exposed portion of the layer
18
is subjected to an etching process, such as a chemical or plasma etch, which removes the layer
18
generally within the open region
16
. It is desirable that the layer
18
be completely removed, substantially exposing an underlying or stop layer
19
. The via
10
is subsequently filled with, for example, a conductive material, such as a metal, to provide electrical communication with the underlying layer
19
.
In
FIG. 2
, the via
10
has been formed by selectively exposing the device
14
to an etching process. Those skilled in the art will appreciate that the duration of the etching process may vary depending upon, among other things, the thickness of the layer
18
. Generally, the duration of the etching process is an engineering design decision based on approximations that may not adequately account for the non-uniformity of the layer
18
and other processing variables, such as wafer coverage of the layer
18
, the non-uniformity of the etching process, and the like. In this embodiment, a portion of the stop layer
19
has been removed during the etching process. The degree to which the etching process is continued after the layer
18
is completely removed is called overetch. The amount of overetch is illustrated by the distance “X.”
In
FIG. 3
, the via
10
has been formed by selectively exposing the device
14
to an etching process. Again, the duration of the etching process may be an engineering design decision based on approximations. In this embodiment, a portion of the layer
18
was not removed from the via
10
. The degree to which the layer 18 is not completely removed is called incomplete etch. The amount of incomplete etch is illustrated by the distance “Y.”
Unfortunately, because of the possible non-uniformity and other processing variables, determining duration times for various etching processes is extremely difficult. Generally, when processing a wafer it is desirable to minimize overetch and incomplete etch. For example, it may be undesirable to overetch unnecessarily because the underlying layer
19
is typically thinned during overetch, which may result in a decreased production yield. In addition, incomplete etch of wafers may also result in a decreased production yield, as electrical communication with the underlying layer
19
may be impaired.
A variety of techniques have been developed to detect the time at which the layer
18
has been substantially removed. One such technique involves detecting the presence of the underlying layer
19
by monitoring the surrounding gases. That is, as the etch process begins to remove the underlying layer
19
, the material from which the layer
19
is constructed begins to appear in the surrounding atmosphere. Once a sufficient amount of this material appears in the atmosphere, it is assumed that the overlying layer
18
has been substantially removed.
As shown in
FIG. 4
, a top view of a wafer
30
illustrates that, while thousands of vias
10
may be present on a wafer
30
, they collectively account for a very small portion of the surface area of the wafer
30
. In some instances, the vias
10
account for substantially less than 1% of the wafer surface area. Thus, as the etching of the vias
10
progresses into the underlying layer
19
, a relatively small amount of material from the layer
19
is introduced into the atmosphere. Detecting this small quantity of material from the underlying layer
19
is exacerbated by the introduction of this same material from other sources.
An outer edge
34
of the wafer
10
may have regions where the surface of the underlying layer
19
may be exposed or where the underlying layer
19
is covered by only a relatively thin layer
12
. In fact, in some cases the exposed outer edge
34
may account for 2-3% of the surface area of the wafer
30
. That is, the surface area of the outer edge
34
is substantially greater than the surface area of the vias
10
. Thus, detecting an endpoint of the via etch by detecting the presence of the underlying layer
19
may be difficult because of the relatively small impact that the vias
10
will have on exposing the underlying layer
19
. That is the existence of materials on the outer edge
34
of the wafer
10
that is the same as the material comprising the underlying layer
19
may make endpoint detection difficult during via etching processes.
The present invention is directed to a semiconductor processing method that addresses some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided that is used in processing a semiconductor wafer. The method includes: forming a first process layer; forming a second process layer above the first process layer; forming a first masking layer above at least a portion of the second process layer, leaving an outer edge portion of at least the second process layer exposed; and performing an etching process to remove the outer edge portion of the first and second layers.
In another aspect of the present invention, a method is provided that is used in processing a semiconductor wafer. The method includes: forming a first process layer; forming a first masking layer above at least a portion of the first process layer, the first masking layer having an outer edge; and performing at least one etching process to remove the first process layer extending beyond the edge of the first masking layer.
REFERENCES:
patent: 4648173 (1987-03-01), Malaviya
patent: 5668045 (1997-09-01), Golland et al.
patent: 6117778 (2000-09-01), Jones et al.
patent: 6200887 (2001-03-01), Balasubramaniam et al.
Merriam Webster's Collegiate Dictionary, tenth edition, p. 14.
Iacoponi John A.
Spikes, Jr. Thomas E.
Zhao Ailian
Advanced Micro Devices , Inc.
Chen Kin-Chan
Utech Benjamin L.
Williams Morgan & Amerson
LandOfFree
Method and apparatus for enhancing endpoint detection of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for enhancing endpoint detection of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for enhancing endpoint detection of a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3096637