Semiconductor device manufacturing: process – Electron emitter manufacture
Reexamination Certificate
2002-04-02
2003-07-08
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Electron emitter manufacture
C438S034000, C445S024000
Reexamination Certificate
active
06589803
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods of fabricating field emission arrays including planarized grids. Particularly, the present invention relates to field emission array fabrication methods that facilitate optimization of the size of grid openings above each of the emitter tips thereof. The present invention also relates to field emission arrays fabricated in accordance with the method of the present invention.
2. Background of the Related Art
Typically, field emission displays (“FEDs”) include an array of pixels, each of which includes one or more substantially conical emitter tips. The array of pixels of a field emission display is typically referred to as a field emission array. Each of the emitter tips is electrically connected to a negative voltage source by means of a cathode conductor line, which is also typically referred to as a column line.
Another set of electrically conductive lines, which are typically referred to as row lines or as gate lines, extends over the pixels of the field emission array. Row lines typically extend across a field emission display substantially perpendicularly to the direction in which the column lines extend. Accordingly, the paths of a row line and of a column line typically cross proximate (e.g., above and below, respectively) the location of an emitter tip. The row lines of a field emission array are electrically connected to a relatively positive voltage source. Thus, as a voltage is applied across the column line and the row line, electrons are emitted by the emitter tips and accelerated through an opening in the row line.
As electrons are emitted by emitter tips and accelerate past the row line that extends over the pixel, the electrons are directed toward a corresponding pixel of a relatively positively charged electro-luminescent panel of the field emission display, which is spaced apart from and substantially parallel to the field emission array. As electrons impact a pixel of the electro-luminescent panel, the pixel is illuminated. The degree to which the pixel is illuminated depends upon the number of electrons that impact the pixel.
An exemplary method of fabricating field emission arrays is taught in U.S. Pat. No. 5,372,973 (hereinafter “the '973 patent”), issued to Trung T. Doan et al. on Dec. 13, 1994. The field emission array fabrication method of the '973 patent includes an electrically conductive grid, or gate, disposed over the surface thereof and including apertures substantially above each of the emitter tips of the field emission array. While the electrically conductive grid of the field emission array disclosed in the '973 patent is fabricated from an electrically conductive material such as chromium, field emission arrays that include grids of semiconductive material, such as silicon, are also known. Known processes, including chemical mechanical planarization (“CMP”) and a subsequent mask and etch, are employed to provide a substantially planar grid surface and to define grid openings or apertures therethrough, which are positioned above each of the emitter tips.
The process of the '973 patent is, however, somewhat undesirable in that upon optimization of either the thickness of the dielectric layer or the diameters of the grid openings, the other may not be optimized. Moreover, as the process of the '973 patent employs layers of dielectric material that are subsequently covered by a grid material without any intervening process steps (e.g., planarization of any imperfections and disposal of another layer of dielectric material thereover), electrically conductive imperfections that may extend through the dielectric material from the substrate to the grid are typically not removed by intervening process steps.
Accordingly, there is a need for a field emission array fabrication process that facilitates optimization of both the diameter of grid openings and the thickness of the dielectric layer thereof. There is also a need for a field emission array fabrication process that reduces the incidence of electrically conductive imperfections that extend from the substrate to the grid and that, thereby, reduces the likelihood of electrical shorts during use of the field emission array.
SUMMARY OF THE INVENTION
The present invention includes a method of fabricating field emission arrays that include planarized grids. The field emission array fabrication method of the present invention employs two dielectric layer disposition processes and two planarization processes on the dielectric layers to facilitate optimization of the size of the grid openings above each of the emitter tips thereof.
According to the present invention, the column lines, emitter tips, and their associated electrical componentry may be fabricated by known processes. A layer of dielectric material, which is also referred to herein as a first layer or as a first dielectric layer, is then disposed over the substrate and the emitter tips. The thickness of the layer of dielectric material is preferably less than the height of the emitter tips. Known processes, such as chemical vapor deposition techniques or oxide growth processes, may be employed to dispose the layer of dielectric material over the substrate and the emitter tips.
Another layer, which is also referred to herein as a second layer, and which includes a material that is preferably planarizable and that is selectively etchable with respect to the dielectric material of the underlying layer and with respect to the material of the substrate and emitter tips, is disposed over the layer of dielectric material. The planarizable, selectively etchable layer may be disposed over the layer of dielectric material by known processes, such as by physical vapor deposition or chemical vapor deposition.
The second layer may be planarized by known processes, such as by chemical-mechanical planarization or chemical-mechanical polishing (“CMP”). Upon planarization of the second layer, portions of the first layer disposed above each of the emitter tips are preferably exposed through the second layer.
Dielectric material of the exposed portions of the first layer may be removed from the top portions of the emitter tips by known processes. For example, the second layer may be employed as an etch mask and the dielectric material of the first layer exposed through the second layer may be etched substantially from at least the top portions of the emitter tips by known processes and with known etchants that will remove the dielectric material with selectivity over the material of the second layer. Alternatively, a mask may be disposed over the field emission array as known in the art, and the dielectric material that is exposed through the second layer may be removed by known etching processes. Preferably, the etchants employed to remove dielectric material from the emitter tips will remove the dielectric material with selectivity over the material of the emitter tips.
The material of the second layer may be removed from above the first layer. As the material of the second layer is removed, electrical imperfections, such as conductive paths (e.g., pieces of metal or holes) through the dielectric material of the first layer, which are also referred to herein as defects, are preferably confined to the first layer.
Another layer of dielectric material, which is also referred to herein as a third layer or as a second dielectric layer, may be disposed over the first layer and over the exposed portions of the emitter tips. The combined thicknesses of the first layer and the third layer are preferably substantially the same as a desired dielectric layer thickness of the field emission array. As the thickness of the third layer, at least in part, determines the size (e.g., diameter) of the grid openings over each of the emitter tips, the thickness of the third layer preferably corresponds to a desired size of the grid openings. Known dielectric material deposition techniques, such as chemical vapor deposition, may be employed to dispose the third l
Micro)n Technology, Inc.
Nguyen Tuan H.
TraskBritt
LandOfFree
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