Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Nonlinear amplifying circuit
Reexamination Certificate
2002-09-05
2003-12-02
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Nonlinear amplifying circuit
C327S561000, C327S335000, C330S253000, C330S291000
Reexamination Certificate
active
06657486
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a MOS differential amplifier circuit, and more particularly to a voltage subtractor/adder circuit formed on a semiconductor integrated circuit device and a MOS differential amplifier circuit which realizes such voltage subtractor/adder circuit and which has linear transconductance.
BACKGROUND OF THE INVENTION
FIG. 17
shows a conventional voltage subtractor/adder circuit described in a publication (IEEE Journal of Solid-State Circuits, Vol. CAS-32, No. 11, pp.1097-1104, November 1985). The circuit of
FIG. 17
comprises two sets of MOS differential pairs. One of the MOS differential pairs comprises MOS transistors M
1
and M
2
, and the other of the MOS differential pairs comprises MOS transistors M
3
and M
4
. Each of the MOS differential pairs is driven by a tail current Iss.
In the voltage subtractor/adder circuit shown in
FIG. 17
, voltages V
1
and V
2
are applied to the gates of the transistors M
1
and M
4
, respectively, of the two sets of MOS differential pairs. Both the transistors M
2
and M
3
are diode-coupled and are driven by a common constant current source (Iss).
Here, with respect to the two sets of MOS differential pairs, tail current values of respective MOS differential pairs and a current value of a constant current source which drives the diode-coupled transistors M
2
and M
3
are all the same. Therefore, the following formulas are obtained.
I
D1
+I
D2
=Iss
(1)
I
D3
+I
D4
=Iss
(2)
I
D2
+I
D3
=Iss
(3)
where, I
D1
, I
D2
, I
D3
and I
D4
designates drain currents of the transistors M
1
, M
2
, M
3
and M
4
, respectively. Therefore, the following relations are also obtained.
I
D1
=I
D3
(4)
I
D2
=I
D4
(5)
That is, since the currents flowing through the transistors M
1
and M
2
are equal to the currents flowing through the transistors M
3
and M
4
, respectively, the differential input voltages of the two sets of MOS differential pairs become equal to each other. Therefore, assuming that a common gate potential of the diode-coupled transistors M
2
and M
3
is V
0
, the following relation exists.
V
1
−V
0
=V
0
−V
2
(6)
That is, the following formula is obtained.
V
0
=
V
1
+
V
2
2
(
7
)
From this formula, it can be seen that the circuit shown in
FIG. 17
functions as a voltage adder circuit. In this case, the differential input voltage of each of the MOS differential pairs becomes as follows:
V
1
-
V
0
=
V
0
-
V
2
=
V
1
-
V
2
2
(
8
)
Next, drain currents I
D1
and I
D4
of the transistors M
1
and M
4
, respectively, of the MOS differential pairs will be derived.
Neglecting the body effect and the channel length modulation, and assuming that the relationship between a drain current and a gate-source voltage of a MOS transistor operating in saturation region follows the square-law, the drain current of a MOS transistor can be represented as follows:
I
D
=&bgr;(
V
GS
−V
TH
)
2
(
V
GS
≧V
TH
) (9a)
I
D
=0(
V
GS
≦V
TH
) (9b)
Here, &bgr;=&mgr;(C
OX
/2)(W/L) is a transconductance parameter, &mgr; is an effective mobility of carrier, C
OX
is capacitance of a gate oxide film per unit area, W is a gate width, L is a gate length, and V
TH
is the threshold voltage of a MOS transistor.
Assuming that the MOS transistors are matched well, the drain currents of the transistors M
1
and M
4
become as follows:
{
I
D1
=
1
2
{
I
SS
+
β
V
i
2
2
I
SS
β
-
V
i
2
4
}
(
&LeftBracketingBar;
V
i
&RightBracketingBar;
≤
2
I
SS
β
)
(
10
a
)
I
D1
=
1
2
I
SS
sgn
(
V
i
)
(
&LeftBracketingBar;
V
i
&RightBracketingBar;
≥
2
I
SS
β
)
(
10
b
)
{
I
D4
=
1
2
{
I
SS
+
β
V
i
2
2
I
SS
β
-
V
i
2
4
}
(
&LeftBracketingBar;
V
i
&RightBracketingBar;
≤
2
I
SS
β
)
(
11
a
)
I
D4
=
1
2
I
SS
sgn
(
V
i
)
(
&LeftBracketingBar;
V
i
&RightBracketingBar;
≥
2
I
SS
β
)
(
11
b
)
where,
Vi=V
1
−V
2
(12)
Therefore, the circuit shown in
FIG. 17
also functions as a voltage subtractor circuit. That is, the circuit shown in
FIG. 17
is a voltage subtractor/adder circuit.
An explanation will now be made on a MOS differential amplifier circuit which has linear transconductance.
FIG. 18
shows a general structure of this type of MOS differential amplifier circuit which is disclosed in Japanese patent laid-open publication No. 7-127887. The circuit of
FIG. 18
comprises a MOS differential pair having MOS transistors M
1
and M
2
which are driven by a tail current Iss (=I
0
+&bgr;Vi
2
/2).
Assuming that the MOS transistors are matched well, a differential output current &Dgr;I
D
=I
D1
−I
D2
of the MOS differential pair comprising the transistors M
1
and M
2
becomes as follows:
{
&AutoLeftMatch;
Δ
I
D
=
β
V
i
2
I
SS
β
-
V
i
2
(
&LeftBracketingBar;
V
i
&RightBracketingBar;
≤
I
SS
β
)
(
13
a
)
Δ
I
D
=
I
SS
sgn
(
V
i
)
(
&LeftBracketingBar;
V
i
&RightBracketingBar;
≥
I
SS
β
)
(
13
b
)
Therefore, when the value within {square root over ( )} in the formula (13a) is a constant value, the differential output current &Dgr;I
D
of the MOS differential pair becomes linear. That is, the condition of the tail current in an adaptive-biasing differential pair becomes as follows:
I
SS
=
I
0
+
1
2
β
V
i
2
(
14
)
Therefore, by driving a MOS differential pair by using a tail current which has a square-law characteristic of an input voltage, it is possible to completely compensate transconductance of the MOS differential pair. The method of driving a MOS differential pair by using a current which varies dynamically such that the transconductance becomes linear is called an adaptive-biasing method. Also, the differential pair which has a linear transconductance obtained in this way is called an adaptive-biasing differential pair.
FIG. 19
shows an example of a concrete circuit of an adaptive-biasing differential pair in which a tail current is supplied thereto by using quadri-tail cell as a squaring circuit.
An output current I
L
of an output of the quadri-tail cell shown in
FIG. 19
can be obtained as follows:
I
L
=I
D3
+I
D4
(15)
{
&AutoLeftMatch;
I
L
=
I
0
4
-
β
V
i
2
4
(
&LeftBracketingBar;
V
i
&RightBracketingBar;
≤
2
I
0
3
β
)
(
15
a
)
I
L
=
2
3
-
I
0
β
V
i
2
+
2
β
&LeftBracketingBar;
V
i
&RightBracketingBar;
2
(
6
I
0
β
-
V
i
2
)
18
(
2
I
0
3
β
≤
&LeftBracketingBar;
V
i
&RightBracketingBar;
≤
2
I
0
β
)
(
15
b
)
I
L
=
0
(
&LeftBracketingBar;
V
i
&RightBracketingBar;
≥
2
I
0
β
)
)
(
15
c
)
Therefore, it is possible to obtain a square-law current.
In order to adaptively bias a MOS differential pair by driving the MOS differential pair by using the output current of the quadri-tail cell, it is possible to set the tail current as determined by the following formula:
Iss=
2
I
0
−2
I
L
(16)
By setting the tail current in accordance with the above formula, transconductance becomes a constant value g
m
={square root over ( )}{(2I
0
/&bgr;}, in a range of an input voltage |Vi|≦{square root over ( )}{(2I
0
)/(3&bgr;)}.
A differe
NEC Electronics Corporation
Nguyen Minh
Sughrue & Mion, PLLC
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