Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2001-12-21
2003-05-06
Lebentritt, Michael S. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S011000, C257S014000, C257S183100, C257S201000
Reexamination Certificate
active
06559470
ABSTRACT:
The present application is also related to the following applications, all of which are filed simultaneously herewith, and which are hereby incorporated by reference as if fully set forth herein:
An application entitled “INSULATED-GATE FIELD EFFECT TRANSISTOR INTEGRATED WITH NEGATIVE DIFFERENTIAL RESISTANCE (NDR) FET”; Ser. No. 10/028,084; and
An application entitled “MEMORY CELL UTILIZING NEGATIVE DIFFERENTIAL RESISTANCE FIELD-EFFECT TRANSISTORS”; Ser. No. 10/029,077; and
An application entitled “DUAL MODE FET & LOGIC CIRCUIT HAVING NEGATIVE DIFFERENTIAL RESISTANCE MODE”; Ser. No. 10/028,394.
An application entitled “CHARGE PUMP FOR NEGATIVE DIFFERENTIAL RESISTANCE TRANSISTOR”; Ser. No. 10/028,089.
FIELD OF THE INVENTION
This invention relates to semiconductor devices and more particularly to an improved negative differential resistance (NDR) FET and circuits that utilize the same. The present invention is applicable to a wide range of semiconductor integrated circuits, particularly for applications where it is desirable to integrate NDR FET devices with conventional FETs and other similar logic/memory circuits, including in SOI and memory applications.
BACKGROUND OF THE INVENTION
A new type of CMOS compatible, NDR capable FET is disclosed in the following King et al. applications: CIP Ser. No. 09/603,101 entitled “A CMOS-PROCESS COMPATIBLE, TUNABLE NDR NEGATIVE DIFFERENTIAL RESISTANCE) DEVICE AND METHOD OF OPERATING SAME”; and which is a C-I-P Ser. No. 09/603,102 entitled “CHARGE TRAPPING DEVICE AND METHOD FOR IMPLEMENTING A TRANSISTOR HAVING A NEGATIVE DIFFERENTIAL RESISTANCE MODE”; and which is a C-I-P Ser. No. 09/602,658 entitled “CMOS COMPATIBLE PROCESS FOR MAKING A TUNABLE NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE all of which were filed Jun. 22, 2000 and which are hereby incorporated by reference as if fully set forth herein. The advantages of such device are well set out in such materials, and are not repeated here.
In preferred embodiments, this device typically uses a dielectric layer for creating a charge trapping region that rapidly traps/detraps charge carriers. A number of different techniques are explained for forming said traps to achieve a desired NDR effect. It is apparent, nonetheless, that additional processing technique (and/or more optimized versions of the processes described in King et al) would be beneficial for expanding the availability fo such devices.
A current trend also is to use so called silicon-on-insulator substrates to manufacture integrated circuits. It is expected that this technology will experience rapid growth in the years to come, but to date, only two terminal NDR diodes have been implemented in such environments. Thus, there is clearly a need for an NDR device that is as easy to integrate as a conventional FET in such technology.
Another growing trend is the use of NDR devices as load elements in SRAM memory cells and other circuit applications. To date, such NDR devices have been limited to two terminal, diode type structures which have operational limitations as well as integration complexities with CMOS processing. Furthermore, it is not possible, for example, to implement a low power memory cell using a single channel technology; current approaches are limited to conventional CMOS, where both p and n type transistors are required. Accordingly, there is an apparent compelling need for a low cost, easily integrable NDR solution for such applications as well.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to overcome the aforementioned deficiencies in the prior art;
Another object of the present invention is to provide an NDR FET that includes additional variations and improvements over the NDR FET described in King et. al.;
Still a further object of the present invention is to provide an additional type of trapping layer, and/or new types of charge traps that can be used advantageously in an NDR FET;
Another object of the present invention is to provide an NDR FET that is embodied within an SOI substrate;
Still a further object of the present invention is to provide a new type of general low power, single channel technology for effectuating logic and memory circuits;
Yet another object of the present invention is to provide an improved type of NDR device that is more flexible and more easily integrated (than prior NDR diode devices) into conventional semiconductor circuits, including SRAM memory cells.
These and other objects are provided by a first aspect of the present invention, which includes a semiconductor structure comprising a semiconductor substrate, and a dielectric layer (gate insulation layer) located on the semiconductor substrate, such that an interface region is formed between the semiconductor substrate and the dielectric layer. A plurality of carrier trapping sites within the interface region are configured for trapping carriers that are electrically biased by an electrical control field to move from a channel into the interface region. Thus, a current in the channel varies from a first current value associated with a conducting condition, to a second current value associated with a non-conducting condition, where the second current value is substantially less than the first current value.
In a preferred embodiment, a trap energy level for the trapping sites in the interface region is higher than a conduction band edge of the channel. Furthermore, the trap energy level is set so that said trapping sites trap primarily hot carriers (and not normal carriers) flowing in the channel to avoid interfering with the operation of the FET. To achieve this result, a trap energy level is set to approximately 0.5 eV higher than the conduction band edge. The semiconductor structure is incorporated as part of an insulated gate field effect transistor which otherwise behaves like a conventional FET in a first region of operation, but yet has NDR capability in a second region of operation.
In the preferred embodiment, the hot carriers tunnel from the channel to the trapping sites, but they are not energized to tunnel from the channel to a conduction band of the interface region. Nor is the interface region required to have a matching conduction band to facilitate a tunneling process, as required in conventional NDR devices.
Further in a preferred embodiment, an NDR FET shares one or more common structures with a conventional insulated gate field effect transistor (IGFET), so that a common set of processing operations can be used to manufacture both types of elements for an integrated circuit.
In other variations, the trapping sites can include water based traps created by a steam ambient. The NDR FET uses an n-type channel implanted with a p-type dopant so that a relatively large electric bias field can be set up to facilitate moving said carriers from said channel to said trapping sites.
In another aspect of the invention, a memory cell includes at least one first dopant type channel insulated gate field effect transistor (IGFET). The first-channel type IGFET has an IGFET gate terminal, an IGFET source terminal connected to a first potential, and an IGFET drain terminal coupled to a storage node. In lieu of a conventional two terminal diode, the present invention incorporates a negative differential resistance field-effect transistor (NDR-FET) element that also has a first dopant-type channel, and acts as a pull up or pull down device when connected in series with the IGFET. The NDR FET element includes a firstNDR FET drain terminal connected to a second potential, a second NDR source terminal connected to the storage node, and a third NDR gate terminal connected to a bias voltage. In this fashion the memory cell is formed entirely of active devices having a common channel dopant type.
In a preferred embodiment, the NDR FET element and the IGFET share at least a common substrate and a common gate insulation layer. In addition, a common gate terminal for both can be fabricated from a single conductive layer. The two devices can further share one or more source/drain regions.
In this fashion, an ND
Gross J. Nicholas
Lebentritt Michael S.
Progressed Technologies, Inc.
LandOfFree
Negative differential resistance field effect transistor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Negative differential resistance field effect transistor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Negative differential resistance field effect transistor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3093536