Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2001-12-20
2003-09-23
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S193000, C365S230030
Reexamination Certificate
active
06625049
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to packaging configurations for integrated circuit devices (ICs) and more particularly to an improvement to the design of a memory array which requires fewer random access memories (RAMs) to be turned on during a read or write cycle than present designs, thereby using less current.
BACKGROUND OF THE INVENTION
Current generation single in-line memory modules (SIMMs) for certain brands of computers use eight one-megabit (1M) dynamic random access memories (DRAMs) arranged in a ×1 configuration (having one data out signal), which supplies the computer with one megabyte (MB) of memory. Since the DRAMs are arranged in a ×1 configuration, one data bit can be extracted from each chip at a time. When a module with eight 1M×1 DRAMs is installed in a computer capable of handling eight bits of data at a time (i.e. an 8-bit computer), it accesses one bit location from each of eight DRAMs on a module simultaneously, thereby receiving eight bits of data. In 16-bit computers, modules containing eight 1M×1 DRAMs are installed in groups of two in the computer. To obtain 16 bits of data all 16 DRAMs are accessed simultaneously, and the computer receives one bit of data from each DRAM for a total of 16 data bits. Each time a 1M×1 DRAM is accessed, it requires about 80 mA of current to be supplied. To access the 16 DRAMs simultaneously requires approximately 640 ma of current per module, or 1,280 mA total.
Some SIMMs use 1M×4 DRAMs, with each DRAM having four bits of data. A module using two 1M×4 chips supplies 1MB of memory, as does a module using eight 1M×1 chips. A module with two 1M×4 devices is functionally equivalent to a module using eight 1M×1 devices, but has fewer parts, thereby being easier to assemble and somewhat more reliable due to fewer solder joints. There is not much power savings using a module with two 1M×4 DRAMs over a module using eight 1M×1 DRAMs, as all the devices on either module are turned on each time one of the devices is accessed in order to access eight data bits, and to access two 1M×4 DRAMs requires about as much power as accessing eight 1M×1 DRAMs.
In most computers, addressed words are an even number of bits, such as eight, sixteen or thirty-two bits. This fits into memory array blocks which use ×4 chips but the arrangement is complicated by the fact that a system of memory parity has proven to be very effective in error detection. The parity is an additional bit for each word, so that an eight bit word (“byte”) is addressed as nine bits, the ninth bit being parity.
Reducing power consumption in a computer or other electronic device is a design goal, as overtaxing a computer's power supply is a common concern. With the addition of modem cards, memory boards, graphics cards, hard disk controller cards, printer buffer cards, and mouse cards, the chances of burning out the computer's power supply from drawing too much current becomes a possibility. Even if the power supply is not unduly stressed, a component which uses more power than a similar component will release more heat, thereby increasing the temperature of the component as well as the inside of the computer or electronic device. Elevated temperatures within the component or within the chassis of a computer can cause other components in the computer to operate more slowly or to fail prematurely.
Reducing the amount of current used by the components in a computer is also a concern to designers of portable computers. The length of time between battery recharges for various brands and types of computers ranges from about two hours to 12 hours. Reducing the amount of current the computer uses, thereby extending the length of time the computer can-be run off the battery, is a design concern as well as a marketing concern.
Reducing the power consumption of components installed in a computer is a goal of computer component designers and computer manufacturers.
SUMMARY OF THE INVENTIONS
An object of this invention is to provide a memory array which uses less power than previous arrays.
This object of the present invention is attained by fabricating an array using a number of memory chips, where, for example, each memory chip can be accessed independently, and where only the DRAM or DRAMs accessed is turned on while all other DRAMs remain in standby mode. A DRAM in standby mode uses much less current than activating the DRAM.
The invention can be applied to modules using DRAMs with multiple data out lines (DQ's). For instance, if a module supplying 1MB of memory contains eight 1M×1 DRAMs is installed in an 8-bit computer, all eight DRAMs would have to be accessed simultaneously to supply the computer with 8 bits of data. On a 1MB module using eight 256K×4, only two DRAMs would have to be accessed to supply the 8-bit computer with 8 bits of data.
Chips containing ×16 data widths have recently been developed by Micron Technology, Inc. To manufacture these 64K×16 DRAMs, a current generation 1M die is packaged with 16 DQ pins to provide a chip in a 64K×16 configuration. Each of the 1,048,576 bits are uniquely addressed through the 16 address bits multiplexed on eight address lines (A
0
-A
7
) during a read or a write cycle.
A common memory configuration supplying 16 bits of data is to use two modules with each module comprising eight 1M×1 devices. A read cycle from two of these modules, as stated previously, requires about 640 mA of current. A functional equivalent of these modules would be two modules with each module comprising eight 64K×16 DRAMs. If these equivalent modules not comprising the invention are used, all 16 DRAMs would be turned on during a read cycle, even though the desired data comes from a single DRAM. A read would require 1280 mA of current. A module of this type comprising the invention, however, would enable only one DRAM during a read, thereby using about 90 mA of current.
When used in applications where an additional bit is used, as for parity, the additional bit may be incorporated into the multiple data out (DQ) architecture as an additional DQ connection. Alternatively, partially operational DRAMs may be used, provided at least one good sector may be addressed.
A module of this type would have signals conforming to JEDEC standards or, in custom uses, to specifications specific to the intended use of the module. In any case, a module containing eight 64K×16 devices would require one CAS line and eight RAS lines. The CAS line selects the desired column number in each of the eight DRAMs. The RAS lines are used as a bank select with each RAS line being used only by a single device, thereby accessing a row address from a single DRAM.
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Ho Hoai
Martin Kevin D.
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