Data processing: software development – installation – and managem – Software program development tool – Translation of code
Reexamination Certificate
1999-11-08
2003-05-20
Khatri, Anil (Department: 2122)
Data processing: software development, installation, and managem
Software program development tool
Translation of code
C717S155000, C717S156000, C714S035000
Reexamination Certificate
active
06567975
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention pertains generally to software prefetching algorithms. More particularly, the invention is a software method and apparatus for inserting prefetch operations according to data flow analysis and, in particular, according to memory operations and associated address forming operations within the program code under consideration.
2. The Prior Art
Current computer systems include, among other things, a memory system and a processing unit (or processor or central processing unit (CPU)). A memory system serves as a repository of information, while the CPU accesses information from the memory system, operates on it, and stores it back.
However, it is well known that CPU clock speeds are increasing at a faster rate than memory speeds. When a processor attempts to read a memory location from the memory system, the request is “very urgent”. That is, in most computer systems, the processor stalls or waits while the memory system provides the data requested to the CPU. The “latency” of the memory is the delay from when the CPU first requests data from memory until that data arrives and is available for use by the CPU.
A cache is a special high-speed memory in addition to the conventional memory (or main memory).
FIG. 1
depicts a conventional hierarchical memory system, where a CPU is operatively coupled to a cache, and the cache is operatively coupled to the main memory. By placing the cache (very fast memory) in front of the main memory (large, slow memory), the memory system is able to satisfy most requests from the CPU at the speed of the cache, thereby reducing the overall latency of the system.
When the data requested by the CPU is in the cache (known as a “hit”), the request is satisfied at the speed of the cache. However, when the data requested by the CPU is not in the cache (known as a “miss”), the CPU must wait until the data is provided from the slower main memory to the cache, and then to the CPU, resulting in greater latency.
To address the problem of latency and to increase the “hit” to “miss” ratio associated with cache memory, many modern computer systems have introduced instructions for prefetching data from memory to cache. For example, instructions set architectures (ISA's), such as SPARC™ V9, support software data prefetch operations. The details of the implementing prefetch operations have been left to the designers of optimizing compilers to find ways to reduce the frequency of cache misses.
One such implementation deals with reducing cache misses associated with loops structures. For example, the following sets forth a portion of code including a loop:
Loop:
Ld [R1], R2
Fadd R2, R3, R4
St R4, [R1]
Add R1, 4, R1
. . .
bcc loop
During compilation of the above code, the loop-based prefetching algorithm will recognize the loop structure and ascertain that the add instruction (Add R1, 4, R1) increments register “R1” over and over. The loop-based prefetching algorithm will also recognize that the register “R1” is used as an address location for the two memory operations (“Ld [R1], R2” and “St R4, [R1]”). From the loop structure, the loop-based prefetching algorithm determines that during the next iteration, the load instruction will be for “Ld [R1+4], R2”. Thus, the loop-based prefetching algorithm may insert an instruction or operation to prefetch the value of a register for a later iteration (e.g., prefetch [R1+4]) during the current iteration, so that when the later iteration is carried out, the value at address R1+4 is in cache.
While useful for loops, the above algorithm is not particularly advantageous for programs without loops or other general purpose programs having complex indirect address references such as pointers, for example. Additionally for highly memory-intensive programs, a solution with analyzes the data flow of the program and inserts the data prefetching operations with respect to an address forming operation and an associated memory operation for the address would be would be particularly beneficial in reducing the frequency of cache misses, thereby increasing the overall speed of the program.
Accordingly, there is a need for a method and apparatus which provides for software prefetching insertion using data flow analysis. The present invention satisfies these needs, as well as others, and generally overcomes the deficiencies found in the background art.
An object of the invention is to provide a method and apparatus for inserting software prefetching operations which overcomes the deficiencies of the prior art.
Another object of the invention is to provide a method and apparatus for inserting software prefetching operations incorporates data flow analysis with respect to memory operations and address forming operations.
Further objects and advantages of the invention will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing the preferred embodiment of the invention without placing limitations thereon.
BRIEF DESCRIPTION OF THE INVENTION
The present invention is a method and apparatus embodied in software suitable for use with compilation of source code. The invention further relates to machine readable media on which are stored embodiments of the present invention. It is contemplated that any media suitable for retrieving instructions is within the scope of the present invention. By way of example, such media may take the form of magnetic, optical, or semiconductor media.
The present invention also relates to a method and use of prefetch operations to load data from memory into a cache. It is contemplated that the invention may be used for loading data from conventional main memory as well as other “slow” data storage structures such as a disk storage or a network storage, for example. Although, the invention is described herein with respect to a single cache, it is contemplated that any suitable cache arrangement (e.g., various levels of cache) is within the scope of the present invention.
In its most general terms, the invention comprises software for inserting prefetch operations based the relative “distance” between an address forming operation and an associated memory operation on the address. The invention is generally used in conjunction and incorporated into compilation software (compiler), which converts source code into a compiled program (or executable file). During compilation, the source code is converted into an intermediary “program code” which is processed by the compiler. After the compiler has completed processing the program code, a compiled program is generated from the program code.
More particularly, the invention is embodied in a data flow prefetch component having a memory operation locate routine, an address forming operation locate routine, a data flow analysis routine, and a prefetch insert routine.
The memory operation locate routine carries out the operation of finding memory operations (or other prefetchable operation) within the program code under consideration. For example, the memory operation locate routine ascertains or otherwise finds each load or store operation. Each memory operation located by the memory operation locate routine is then processed by the address forming operation locate routine.
The address forming operation locate routine carries out the operation of finding an address forming code sequence associated with a memory operation. In general, for a given memory operation (or other prefetchable operation) located by the memory operation locate routine, the address forming operation locate routine performs a backward dataflow pass from the memory operation. For example, one way to form an address is to place a name of an address location into a register location. Another example of an address forming operation may include indirectly loading address location from a pointer data structure into a register location. Other conventional address forming operations are well known i
Khatri Anil
Martine & Penilla LLP
Sun Microsystems Inc.
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