Micro-processor

Details Micro-processor Micro-processor

1999-11-24

2003-08-12

Pan, Daniel H. (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction fetching

Prefetching

C712S237000, C711S213000, C711S144000, C710S052000, C710S054000

Reexamination Certificate

active

06606701

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a data processing apparatus, and more particularly to a micro-processor having a bus interface function.
2. Description of the Related Art
A cache memory may be incorporated into a micro-processor for enhancing system performances. Such a micro-processor including a cache memory therein can accomplish its maximum performance when the cache memory is hit, but would have performances the same as or inferior to performances of a system including no cache memory, when the cache memory is incorrectly hit. In particular, it is necessary in a system carrying out real-time control to estimate a process time on the assumption that a memory access performance is at a minimum. Hence, if such a system has to carry out irregular process such as interruption, a hit rate of a cache memory cannot avoid from being reduced, resulting in reduction in performances due to cache—replace.
In a system for carrying out real-time control, there are increased applications which require multi-media processing such as image processing and audio processing. Thus, there is increased a demand for a micro-processor which can carry out both real-time control and data processing. Hence, a system for carrying out real-time control, including no cache memory, is also required to enhance capability of making access to an external memory, an external device, and so on. As a function for enhancing access performance, here is known a burst transfer function.
A pre-fetch queue FIFO
101
fetches and stores therein a command code. A pre-fetch queue valid
103
indicates that an effective command code is stored in the pre-fetch queue FIFO
101
. A queue clear signal
104
is generated when a branch command or interruption is to be carried out, and is transmitted to the pre-fetch queue valid
103
.
A pre-fetch request signal
107
is transmitted from OR circuit
105
to an access priority judging circuit
111
. The pre-fetch request signal
107
is made active when the pre-fetch queue FIFO
101
has a vacancy therein. A queue empty signal
108
is transmitted from an inverter
106
to the access priority judging circuit
111
. The queue empty signal
108
is made active when the pre-fetch queue FIFO
101
is entirely empty. An operand data request signal
109
is transmitted to the access priority judging circuit
111
. The operand data request signal
109
is made active when operand data access
109
a
is generated.
The access priority judging circuit
111
determines a kind of access to be generated next. A bus state control circuit
122
generates a bus state in accordance with access having been determined by the access priority judging circuit
111
.
The bus state control circuit
122
transmits a bus state signal, a T
1
state signal and a T
2
state signal to a bus timing producing circuit
126
in accordance with bus access signals
123
,
124
and
125
. The T
1
state signal first outputs an address and a control signal. The T
2
state signal makes access to a memory, a device and so on, following the T
1
state signal.
The bus state control circuit
122
transmits a priority judging signal
116
to the access priority judging circuit
111
. The priority judging signal
116
is a timing signal for judging a priority of next address.
The bus timing producing circuit
126
generates bus timing signals
127
and
128
in accordance with the T
1
and T
2
state signals
123
and
124
transmitted from the bus state control circuit
122
.
As illustrated in
FIG. 2
, a micro-processor
150
including therein a bus interface having such a structure as illustrated in FIG.
1
and having been explained above is connected to both a first memory
151
and a second memory
152
through a system bus
153
. The first memory
151
has a function of carrying out burst transfer and stores therein a command code. The second memory
152
makes operand data access. For instance, the first memory
151
may be constituted as a read only memory (ROM) having a paging function, or as a synchronous FLASH memory, and the second memory
152
may be constituted as SRAM or DRAM.
Hereinbelow is explained an operation of the above-mentioned bus interface illustrated in FIG.
1
.
When a program is to be carried out in branch, the pre-fetch queue valid
103
is made entirely invalid by means of the queue clear signal
104
, and queue empty signal
108
is made active.
The access priority judging circuit
111
determines a kind of bus access on receipt of the priority judging signal
116
, and transmits a command fetch access signal
113
or an operand data access signal
114
to the bus stat control circuit
122
. The access priority judging circuit
111
activates the operand data access signal
114
when both the pre-fetch request signal
107
and the operand data request signal
109
are received. As an alternative, the access priority judging circuit
111
may be designed to activate the command fetch access signal
113
when the queue empty signal
108
is active.
The bus state control circuit
122
transmits the T
1
state signal, the T
2
state signal and the bus state signal to the bus timing generating circuit
126
in accordance with the bus access signals
123
,
124
and
125
. The bus timing generating circuit
126
makes access to external ROM or RAM, and carries out command fetch access or operand data access.
In burst transfer, there is first generated a state (hereinafter, referred to as “T
1
state”) for outputting an address, a control signal and so on, and subsequently is generated a state (hereinafter, referred to as “T
2
state”) for making access to a memory, a device and so on. If a memory or device fulfills a requirement for carrying out burst transfer when access is to be made to successive addresses in the same memory, only T
2
state is generated for making access to the later address. That is, it would be possible to accomplish high-speed memory access in burst transfer, since T
1
state is not generated in the second or later access in successive access.
Time necessary for generating T
1
or T
2
state is dependent on a specific memory. As an example of a memory having a function of burst transfer, there is a memory which makes use of successive high-speed access to a memory cell associated with a selected address, or a memory having a interleave structure.
In general, a micro-processor carries out a command through the steps of (a) making access to a memory for fetching a command code, (b) storing the command code in a pre-fetch queue, (c) data-aligning the command code, and (d) decoding the command code to thereby identify a command, and carrying out the thus identified command. A micro-processor further carries out the step of (e) making access to a memory for writing data thereinto or reading data out thereof, when a specific command is to be carried out.
In the above-mentioned steps, access to a memory in the step (a) for fetching a command code is called command fetch access, and access to a memory in the step (e) for writing data thereinto or reading data out thereof is called operand data access.
In accordance with command fetch access, since access is to be made successively in an order of address except branching, it would be possible to accomplish high-speed access in burst transfer through the use of a memory having a function of carrying out burst transfer.
On the other hand, operand data access is characterized in that address is seldom successive except that block transfer is to be carried out, and that an interval between addresses is not constant.
Comparing a priority of command fetch access to a priority of operand data access, operand data access has a higher priority. Hence, if a request of operand data access is made while burst transfer of command fetch is being carried out, the burst transfer is interrupted, and operand data access is carried out.
In the conventional micro-processor, if an operand data request
109
is made to another memory while command fetch of T
1
, T
2
, T
2
, T
2
, - - - are successively ma

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