Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-11-07
2003-06-17
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189050
Reexamination Certificate
active
06580645
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a page buffer. In particular, the present invention discloses a page buffer with an improved programming efficiency for a non-volatile memory.
2. Description of the Prior Art
Recently, flash memory technology is quickly developed owing to a great demand for portable electric products. The flash memory related market is also further advancing associated researches into flash memory devices. The portable electric products include digital cameras, cellular phones, video game apparatus, personal digital assistants, electric recorders, and programmable ICs. For example, digital cameras need the flash memory to replace the traditional film, and the cellular phones, video game apparatus, personal digital assistants, electric recorders, and programmable ICs require the flash memory to store data or programs.
The flash memory is a non-volatile memory. That is, the flash memory records data through changing a threshold voltage of a transistor or a memory cell to control a gate channel induced at the transistor or the memory cell. The data stored in the flash memory, therefore, will not be cleared or lost even thought a corresponding operating voltage of the flash memory is turned off. The flash memory is viewed as a special structure of an electrically erasable and programmable read only memory (EEPROM).
Please refer to
FIG. 1
, which is a structure diagram of a prior art EEPROM
10
. EEPROM
10
has a substrate
12
, a source
14
, a drain
16
, a floating gate
18
, and a control gate
20
. The floating gate
18
is separated from a channel
22
positioned in the substrate
12
by an oxide layer
24
. The substrate
12
is electrically connected to a reference voltage Vbb. Generally speaking, a ground voltage is often used as the reference voltage. If the EEPROM
10
has an N-channel metal oxide semiconductor (NMOS) structure, the substrate
12
is a p-doped area, and the source
14
and the drain
16
are n-doped areas. On the contrary, if the EEPROM
10
has a P-channel metal oxide semiconductor (PMOS) structure, the substrate
12
is an n-doped area, and the source
14
and the drain
16
are p-doped areas.
Operation of the EEPROM
10
is briefly described as follows. A voltage Vcg inputted into the control gate
20
is capable of altering the total amount of electrons stored on the floating gate
18
. A threshold voltage related to formation of the channel
22
is affected by the amount of electrons stored on the floating gate
18
. Therefore, the EEPROM
10
senses two states (“0” and “1”) according to the amount of electrons stored on the floating gate
18
while performing a reading operation. The amount of electrons is adjusted by driving electrons from the channel
22
to the floating gate
18
or by expelling electrons from the floating gate
18
. When the floating gate
18
stores more electrons, the threshold voltage related to formation of the channel
22
is increased. On the other hand, when the floating gate
18
stores fewer electrons, the threshold voltage related to formation of the channel
22
is decreased. In order to make the source
14
and the drain
16
of the EEPROM
10
electrically connected, the control voltage Vcg is inputted into the control gate
20
trying to overcome the existing threshold voltage affected by electrons on the floating gate
18
.
Therefore, current passing through the source
14
and the drain
16
is sensed to determine whether a binary digit “0” or a binary digit “1” is stored by the EEPROM
10
. If the control voltage Vcg is high enough to overcome the threshold voltage (fewer electrons stored on the floating gate
18
), the detected current value is high. On the contrary, if the control voltage Vcg is not high enough to overcome the threshold voltage (more electrons stored on the floating gate
18
), the detected current value is low. The data recorded on the EEPROM
10
is easily read owing to different threshold voltages.
For the sake of programming the EEPROM
10
, the total amount of electrons stored on the floating gate
18
must be precisely controlled to obtain a required threshold voltage. A Fowler-Nordheim tunneling or a hot electron injection is normally adopted to control electrons on the floating gate
18
. For example, the hot electron injection is performed by inputting the control voltage Vcg with 10 volts into the control gate
20
, inputting a voltage Vd with 5 volts into the drain
16
, and inputting a ground voltage Vs into the source
14
. When electrons move from the source
14
to the drain
16
via the channel
22
, an electric field built between the control gate
20
and the source
14
and an electric field built between source
14
and the drain
16
accelerate the electrons positioned around the drain
16
so that the electrons will achieve high kinetic energy. In the end, the positive voltage at the control gate
20
will attract electrons that have overcome a potential energy barrier existing in the oxide layer
24
, and pulls electrons up to the floating gate
18
.
The Fowler-Nordheim tunneling is performed by inputting the control voltage Vcg with 7 volts to the control gate
20
, inputting a positive voltage Vs to the source
14
, and floating the drain
16
. An electric field is built between the source
14
and the control gate
20
, and pierces the oxide layer
24
. The electrons positioned on the floating gate
18
are affected by the electric field established between the control gate
20
and the source
14
, and are energized to overcome the potential energy barrier existing in the oxide layer
24
. In the end, the electrons will tunnel through the oxide layer
24
and reach the source
14
. Compared with other memory devices such as a dynamic random access memory (DRAM), the flash memory requires a longer period of time to finish charging and discharging the floating gate
18
to record data. The data access speed of the flash memory, therefore, is limited by the above-mentioned drawback.
Please refer to
FIG. 2
, which is a block diagram of a prior art flash memory device
30
. The flash memory device
30
has a controller
32
, a sense amplifier
34
, a status register
36
, a charge pump circuit
38
, an X decoder
40
, a Y decoder
42
, and a memory
44
. The memory
44
has a plurality of memory cells
46
arranged in a matrix format for storing binary data. The controller
32
is used to control operation of the flash memory device
30
to access each memory cell
46
of the memory
44
. The status register
36
records a current operating status (programming, reading, or erasing) related to the memory
44
.
A computer system, therefore, reads the status register
36
through the controller
32
to decide a succeeding operation suitable to be applied upon the flash memory device
30
. The sense amplifier
34
reads the memory cells
46
, and amplifies a corresponding result detected from the memory cell
46
. The charge pump circuit
38
is used to provide the memory cells
46
with appropriate voltages required for performing programming, reading, or erasing operations. The X decoder
40
and the Y decoder
42
are used to locate each memory cell
46
with an associated memory address such as a specific column and a specific row. Each memory cell
46
does not have exactly the same structure owing to many unexpected variations induced during the semiconductor process. Therefore, the quantity of electrons passing through the oxide layer
24
to the floating gate
18
is not easy to predict and control. In other words, an external voltage such as the control voltage Vcg does not precisely adjust a desired amount of the electrons stored on the floating gate
18
. When the X decoder
40
receives data transmitted from the controller
32
, and decodes the data to locate the memory cell
46
on row n, the Y decoder
42
also receives data transmitted from the controller
32
, and decodes the data to program each memory cell
46
at the same row n according to an associated voltage generated by the charge p
Ho Chien-Hung
Lin Yen-Tai
e-Memory Technology, Inc.
Hsu Winston
Nguyen Tan T.
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