Amplifiers – With semiconductor amplifying device – Including current mirror amplifier
Reexamination Certificate
2002-03-22
2003-07-01
Choe, Henry (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including current mirror amplifier
C323S315000
Reexamination Certificate
active
06587000
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a current mirror circuit and an analog-digital converter. More particularly, the present invention relates to a current mirror circuit and an analog-digital converter, in which a current mirror having a high accuracy can be obtained even at a low power supply voltage.
2. Description of the Related Art
A current mirror circuit is a circuit for sending to a second transistor connected to a first transistor the same current as the current flowing through the first transistor or the proportional current, as if it is a mirror.
Typically, a drain current IDS of a MOS transistor in a saturation region is given by:
I
DS
=(½)×&mgr;×
C
OX
×(
W/L
)×(
V
GS
−V
t
)2×(1
+&lgr;×V
DS
) (1)
In the equation (1), &mgr; is a mobility of a carrier, C
OX
is a thickness of gate oxide film, L is a length of a channel, W is a width of the channel, V
t
is a threshold voltage, V
GS
is a voltage between a gate and a source, V
DS
is a voltage between a drain and the source, and &lgr; is a channel length modulation coefficient.
In the usual current mirror circuit, as indicated by the equation (1), even if the gate-source voltages V
GS
are equal to each other, a drain-to-source voltage V
DS
of an NMOS transistor on an input side is different from that of an NMOS transistor on an output side. For this reason, the channel length modulation effect resulting from the channel length modulation coefficient &lgr; causes a large error to occur between an input current (standard current I
in
) and an output current I
out
. In order to reduce this error resulting from the channel length modulation effect, the counter-plan is typically carried out by designing the current mirror circuit as a cascode connection and the like.
The cascode current mirror circuit is disclosed in, for example, “Analog Integrated Circuit Design Technique, Low Part (1990) p286-288” written by Gray et al. An output resistance of the current mirror circuit can be increased by designing the current mirror circuit as the cascode connection. As a result, it is possible to reduce the error caused by the channel length modulation effect.
As a conventional example of a related current mirror circuit, Japanese Laid Open Patent Application (JP-A 2000-114891) discloses “Current Source Circuit”.
FIG. 1
is a circuit diagram showing the configuration of that current mirror circuit.
A current mirror circuit
101
is provided with an operational amplifier
111
, a constant current source
130
, and N-channel MOS transistors Q
101
, Q
102
and Q
103
. Hereafter, the N-channel MOS transistor is referred to as an NMOS transistor.
A high potential side voltage source (not shown) is connected to one of both terminals of a constant current source
130
, and a power supply voltage V
DD
is inputted/supplied. A drain of the NMOS transistor Q
101
and a non-inverting input terminal of the operational amplifier
111
are connected to the other terminal of the constant current source
130
. The constant current source
130
outputs the standard current I
in
from the other terminal, based on the power supply voltage V
DD
. The drain of the NMOS transistor Q
101
is connected to a gate of the NMOS transistor Q
101
.
A drain of the NMOS transistor Q
102
is connected to an inverting input terminal of the operational amplifier
111
and a source of the NMOS transistor Q
103
. A gate of the NMOS transistor Q
102
is connected to the gate of the NMOS transistor Q
101
. The sources of the NMOS transistor Q
101
and the NMOS transistor Q
102
are grounded.
The gate of the NMOS transistor Q
103
is connected to an output terminal of the operational amplifier
111
. The drain of the NMOS transistor Q
103
is connected to an output terminal Z. The output terminal Z is connected to a load circuit (not shown) An output current I
out
(the voltage between the terminal Z and the ground: the output voltage V
out
) corresponding to the standard current I
in
is supplied through the output terminal Z to the load circuit (not shown).
Due to the operational amplifier
111
, the drain voltage of the NMOS transistor Q
102
is set to be substantially equal to the drain voltage of the NMOS transistor Q
101
. If the drain voltage of the NMOS transistor Q
103
is changed by the variation in the load circuit and the like, the source voltage of the NMOS transistor Q
103
, namely, the drain voltage of the NMOS transistor Q
102
is changed correspondingly to the change. The output voltage of the operational amplifier
111
is also changed on the basis of the change in the drain voltage of the NMOS transistor Q
102
.
For example, if the drain voltage of the NMOS transistor Q
102
is increased and it becomes higher than the drain voltage of the NMOS transistor Q
101
, a voltage difference between the drain voltages of the NMOS transistors Q
101
, Q
102
is generated correspondingly to the increase in the drain voltage of the NMOS transistor Q
102
. The output voltage of the operational amplifier
111
is dropped correspondingly to the voltage difference. Since the threshold voltage of the NMOS transistor Q
103
is constant, the drop in the gate voltage causes the drop in the source voltage, and the drain voltage of the NMOS transistor Q
102
is kept substantially constant. On the other hand, if the drain voltage of the NMOS transistor Q
102
is dropped, and it becomes lower than the drain voltage of the NMOS transistor Q
101
, the output voltage of the operational amplifier
111
is increased correspondingly to the drop in the drain voltage of the NMOS transistor Q
102
. The source voltage of the NMOS transistor Q
103
is increased correspondingly to the increase. Accordingly, this increase suppresses the drop tendency of the drain voltage of the NMOS transistor Q
102
.
As mentioned above, the variation in the drain voltage of the NMOS transistor Q
102
caused by the variation in the load circuit (not shown) connected to the drain of the NMOS transistor Q
103
and the like is suppressed by the operational amplifier
111
. Accordingly, the drain voltage of the NMOS transistor Q
102
is kept at the substantially constant level, namely, at the level equal to the drain voltage of the NMOS transistor Q
101
. If the NMOS transistors Q
101
, Q
102
are under the same condition, for example, if they have the same size and the same carrier mobility, the same current as the NMOS transistor Q
101
flows through the NMOS transistor Q
102
. That is, the output current I
out
substantially equal to the standard current I
in
flows through the drain of the NMOS transistor Q
103
. The output voltage V
out
(the voltage between the terminal Z and the ground) corresponding to the output current I
out
is supplied to the load circuit (not shown).
The current mirror circuit
101
shown in
FIG. 1
can attain the current mirror circuit having the high accuracy since the operational amplifier
111
forcedly makes the drain-to-source voltages of the NMOS transistors Q
101
, Q
102
equal to each other.
According to the above-mentioned technique disclosed in Japanese Laid Open Patent Application (JP-A 2000-114891), it is necessary to operate all the transistors (the NMOS transistors Q
101
, Q
102
and Q
103
) in the saturation region, in order to normally operate the current mirror circuit
101
. That is, it is necessary to operate the NMOS transistors Q
101
, Q
102
and Q
103
under the following condition:
V
DS
>V
GS
−V
t
(2)
The output side in the current mirror circuit
101
is configured as the longitudinal pile (cascode connection) of the two MOS transistors by the NMOS transistors Q
102
, Q
103
. For this reason, for example, when the GND (ground) is used as a standard and the sizes of the transistors (W/L, L: Channel Length, W: Channel Width) are equal to each other, if the substrate effect (back gate effect) is ignored, they are not normally operated unless the value of the output voltage V
out
(the voltage between the terminal Z
Choe Henry
Hayes & Soloway P.C.
NEC Electronics Corporation
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