Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-02-01
2003-08-12
Vanderpuye, Ken (Department: 2732)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S516000
Reexamination Certificate
active
06606324
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention refers to the clock recovery in transport of constant bit rate (CBR) channels, especially suited for the implementation of the adaptation layer of the asynchronous transfer mode (AAL). This adaptation layer is used for transport of CBR services over an ATM network.
More precisely, this invention relates to a method and an apparatus for clock recovery of a CBR service which is transported over a packet-switched network.
Four solutions of the problem of an adaptive clock recovery in transport of CBR services over an ATM are presently known. These methods are classified as “adaptive”, since they do not need a common source of network timing as a reference to recover the remote source clock.
To recover a clock signal by periodically sampling a buffer fill level and adjusting the clock frequency to achieve a steady-state average of the buffer fill level or its derivative is known from WO 95/33 320.
WO 95/22 233 discloses the method of submitting to the first packet from a sequence of packets a predetermined delay, then the fill level of a delay buffer is monitored and subsequent packets are submitted to a variable delay, in order to keep the ill level of said buffer and to minimise the risk of over- or underflow of said buffer.
Furthermore, a time-averaging method and a method of optimal control are reported in IEEE 1988 ref. CH2535-3/86/0000-1468.
The International application PCT/SE 97/01168 in the name of the same Applicant as this application, discloses the recovery of clock frequency of a CBR service carried over a packet-switched network, comprising means for temporarily storing data at receiving end and providing a clock frequency, with which data is polled out from said storage means, and the calculation of a series of time differences.
The latter method is not affected by a few drawbacks of the others and allows a faster and more stable convergence than with said other methods, but it requires calculation means possessing high performances and ensures only a poor recovery of the source clock upon a drift.
SUMMARY OF THE INVENTION
This invention overcomes these drawbacks and makes the convergence still faster by an improved method for the clock recovery in transport of constant bit rate (CBR) channels. Such a method, comprising the steps of: temporarily storing data at receiving end; using a clock frequency, with which data is polled out from said storing means; and calculating a series of time differences, is characterised in that it comprises the further steps: of sending said difference series to a control block where the instant value of said differences is multiplied by the value of its own index; of subsequently comparing the obtained result to the sum of the previous values up to the moment; of checking that the absolute value of the difference outcoming from said comparison is less than the error multiplied by the index of the previous value and by the absolute sum value; and of calculating the control value of the clock correction by dividing the sum value by index and by multiplying the same by gain.
Preferably, the method comprises the further step of recalculating, after application of each correction, the cumulated sum, depending on system requirements, without resetting the index.
The invention relates also to an apparatus for the clock recovery in transport of constant bit rate (CBR) channels, suitable for the implementation of the adaptation layer of the asynchronous transfer mode (AAL, ATM Adaptation Layer), comprising memory means, apt to temporarily store data at the receiving end, a clock set to determine the frequency of data polled out from said memory means, calculation means, to calculate time differences between two consecutive incoming packets, means to reduce noise and means to adjust the frequency at which said clock operates. Such an apparatus is characterised in that it includes a control block which is adapted to carry out the multiplication of the instant value of said differences by its own index; a subsequent comparison with the sum of the value up to the moment; and a check that the absolute value of the difference, resulting from said comparison, is less than the error, multiplied by the index of the previous value and by the absolute value of the sum.
Such apparatus preferably comprises also fast filters and, respectively, slower, more precise filters to be independently utilized and calculation means adapted to calculate the control value of the clock correction, by dividing the sum value by the index and by multiplying the same by the gain.
The same apparatus can also comprise means adapted to recalculate the cumulated sum depending on the requirements of the system, without resetting the index and means adapted to increase error value when a number of corrections which took place previously were reciprocally concordant, and to lower the same when a number of corrections which took place previously were reciprocally discordant.
REFERENCES:
patent: 5784379 (1998-07-01), Tan
patent: 5844891 (1998-12-01), Cox
patent: 5912880 (1999-06-01), Bernstein
patent: 5999533 (1999-12-01), Peres et al.
patent: 6111878 (2000-08-01), Powell
patent: 6252850 (2001-06-01), Lauret
patent: 6400683 (2002-06-01), Jay et al.
patent: 0 394 051 (1990-10-01), None
Ahmed, “Adaptive Terminal Synchronization in Packet Data Networks”, Communications Technology for the 1990's and Beyond, Dallas, Nov. 27-30, 1989, vol. vol. 2, No.—, Institute of Electrical and Electronics Engineers, pp. 728-732.
Ahmed et al, “ATM Circuit Emulation—A Comparison of Recent Techniques”, Countdown to the New Millennium, Phoenix, Dec. 2-5, 1991, vol. vol. 1, No.—, Dec. 2, 1991, Institutes of Electrical and Electronics Engineers, pp. 370-374.
Lau et al, Synchronous Techniques for Timing Recovery in Bison, IEEE Transactions on Communications, vol. 43, No. 2/04, Part 03, Feb. 1, 1995, pp. 1810-1818.
Youn et al, CNV Based Intermedia Synchronization Mechanism Under High Speed Communication Environment, IEICE Transactions on Communications, vol. E76-B, No. 6, Jun. 1, 1993, pp. 634-645.
Nixon & Vanderhye P.C.
Telefonaktiebolaget LM Ericsson (publ)
Vanderpuye Ken
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