Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-01-31
2003-05-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S082000, C438S077000, C438S459000
Reexamination Certificate
active
06559058
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to a process for manufacturing structures on a silicon substrate. More specifically, the present invention relates to creating three-dimensional integrated circuits through a process that uses chemically-selective endpoint detection.
2. Related Art
The dramatic advances in computer system performance during the past 20 years can largely be attributed to improvements in the processes that are used to fabricate integrated circuits. By making use of the latest fabrication processes, integrated circuit designers can presently integrate computing systems comprised of hundreds of millions of transistors onto a single semiconductor die which is a fraction of the size of a human fingernail.
Integrated circuit fabrication technology is also being used to fabricate Micro-Electro-Mechanical Systems (MEMs), such as microscopic motors and other types of actuators, that are invisible to the unaided human eye, and which have dimensions measured in fractions of microns.
A typical fabrication process builds structures through successive cycles of layer deposition and subtractive processing, such as etching. As the dimensions of individual circuit elements (or MEMs structures) continue to decrease, it is becoming necessary to more tightly control the etching operation. For example, in a typical etching process, etching is performed for an amount of time that is estimated by taking into account the time to etch through a layer to reach an underlying layer, and the time to overetch into the underlying layer. However, this process can only be controlled to +/−100 Angstroms, which can be a problem when fine control of dimensions is required.
Furthermore, conventional etching processes that indiscriminately etch all exposed surfaces are not well suited to manufacture some structures that require tighter control over subtractive processing operations. As circuit structures become smaller, there is less tolerance available to account for uncertainties in the manufacturing process.
What is needed is a process that facilitates selective etching to form integrated circuits including denser circuitry without the problems mentioned above.
SUMMARY
One embodiment of the present invention provides a system for using selective etching to form three-dimensional components on a substrate. The system operates by receiving a substrate composed of a first material. Next, a second layer composed of a second material is formed on selected portions of the substrate. A third layer composed of a third material is then formed over the substrate and the second layer. Finally, an etching operation using a selective etchant is used to remove the second layer, thereby leaving the substrate, which forms a first active layer, and leaving the third layer, which forms a second active layer.
In one embodiment of the present invention, the first material is silicon (Si), the second material is silicon-germanium (Si—Ge) or silicon-germanium-carbon (Si—Ge—C), the third material is Si, and the selective etchant is hydrofluoric
itric/acetic (HNA) acids.
In one embodiment of the present invention, the first material is Si—Ge or Si—Ge—C, the second material is Si, the third material is Si—Ge or Si—Ge—C, and the selective etchant is tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH—H
2
O).
In one embodiment of the present invention, the first material is Si—Ge—C, with carbon greater than or equal to one atomic percent, and the selective etchant is TMAH or KOH—H
2
O.
In one embodiment of the present invention, the first material is Si—Ge—C, with carbon less than or equal to one atomic percent, and the selective etchant is TMAH or KOH—H
2
O.
In one embodiment of the present invention, the second layer is an epitaxial layer.
In one embodiment of the present invention, the third layer is an epitaxial layer.
In one embodiment of the present invention, the second layer is formed on selected portions of the substrate by first forming an epitaxial blocking structure on the substrate. Next, a patterning layer is applied over the epitaxial blocking structure. Forming the second layer on exposed portions of the substrate exposed by the patterning layer.
In one embodiment of the present invention, more than two active layers are formed by repeating the steps of forming the second layer, forming the third layer, and performing the etching operation for each additional active layer.
One embodiment of the present invention provides a system for using selective etching to form three-dimensional components on a substrate. The system operates by first receiving a substrate composed of a first material. Next, a second layer composed of a second material is formed on selected portions of the substrate. A third layer composed of a third material is then formed over selected portions of the substrate and the second layer. Next, a fourth layer composed of a fourth material is formed over third material and the remainder of the substrate and the second layer. The second, third and fourth layers are then planarized using chemo-mechanical polishing to create a planarized surface and a fifth layer is deposited. Finally, an etching operation using a selective etchant is performed to remove the second layer, thereby forming a first active layer in the substrate and a second active layer in the fifth layer, whereby the third layer and the fourth layer form vias between the first active layer and the second active layer
In one embodiment of the present invention, the first material is Si, the second material is Si—Ge or Si—Ge—C, the third material is P-type Si, the fourth material is N-type Si, and the selective etchant is HNA.
In one embodiment of the present invention, the second layer is an epitaxial layer.
In one embodiment of the present invention, the second layer is formed on selected portions of the substrate by first forming an epitaxial blocking structure on the substrate. Next, a patterning layer is applied over the epitaxial blocking structure. The second layer is formed on portions of the substrate exposed by the patterning layer.
In one embodiment of the present invention, the third layer is formed on selected portions of the substrate and the second layer by first removing portions of the epitaxial blocking structure and then forming the third layer on exposed portions of the substrate and the second layer.
In one embodiment of the present invention, the fourth layer is formed by first removing the remaining portions of the epitaxial blocking structure and then forming the fourth layer over the third layer, remaining portions of the second layer, and remaining portions of the substrate.
One embodiment of the present invention provides a three-dimensional integrated circuit created using a selective etching process. The three-dimensional integrated circuit includes a substrate composed of a first material, a second layer composed of a second material on selected portions of the substrate, and a third layer composed of a third material over the substrate and the second layer. A selective etchant is used to remove the second layer, thereby forming a first active layer in the substrate of the three-dimensional integrated circuit and forming a second active layer in the third layer of the three-dimensional integrated circuit.
One embodiment of the present invention provides a three-dimensional integrated circuit created using a selective etching process. The three-dimensional integrated circuit includes a substrate composed of a first material, a second layer composed of a second material on selected portions of the substrate, and a third layer composed of a third material on selected portions of the substrate and the second layer, and a fourth layer composed of a fourth material over the third layer and the remainder of the substrate and the second layer. The second layer, third layer, and fourth layer are planarized using chemo-mechanical polishing to create a planarized surface. Next, a fifth layer composed of a fifth material is formed on the planarized surface
Hunt Charles E.
Peterson Jeffrey J.
Luk Olivia
Niebling John F.
Park Vaughan & Fleming LLP
The Regents of the University of California
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