Method of manufacturing a III-V semiconductor gate structure

Details Method of manufacturing a III-V semiconductor gate structure Method of manufacturing a III-V semiconductor gate structure

1994-06-06

1996-01-16

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 39, 437 41, 437176, 437184, 148DIG113, H01L 21338

Patent

active

054847400

ABSTRACT:
A manufacturable III-V semiconductor gate structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.

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patent: 5296398 (1994-03-01), Noda
S. Subbanna et al., "A Novel Borderless Contact/Interconnect Technology Using Aluminum Oxide Etch Stop for High Performance SRAM and Logic", IEEE, 1993, pp. 441-444.
R. D. J. Verhaar et al., "A 25 .mu.m2 Bulk Full CMOS SRAM Cell Technology with Fully Overlapping Contacts", IEEE, 1990, pp. 473-476.

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