Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
1998-01-28
2003-04-08
Christensen, Andrew (Department: 2615)
Television
Camera, system and detail
Solid-state image sensor
C348S312000, C348S282000
Reexamination Certificate
active
06545713
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solid-state image pickup apparatus using a CCD image sensor, and more particularly to an improvement of output characteristics in an output section of such an image sensor.
2. Description of the Related Art
For solid-state image pickup, such as used in TV cameras equipped with a CCD image sensor, scanning timing is set based on synchronization signals in accordance with a predetermined television format. For example, in the NTSC format, the vertical scanning period is set to 1/60 second and the horizontal scanning period is set to 2/525 of the vertical scanning period. The result is that the picture information for a single image plane is output in the form of successive picture signals, one horizontal line at a time.
FIG. 1
is a block diagram showing the basic structure of an image pickup apparatus that uses a CCD image sensor, while
FIGS. 2 and 3
are timing charts illustrating the operations thereof.
A typical frame transfer type CCD image sensor
1
comprises an image pickup portion
1
i
, a storage portion
1
s
, a horizontal transfer section
1
h
, and an output section
1
d
. The image pickup portion
1
i
comprises a plurality of parallelly arranged CCD shift registers, where a plurality of bits follow in succession in the vertical direction. Respective bits of these shift registers form optical pixels and accumulate information charges, which are generated by input light during an image pickup period. The storage portion
1
s
comprises a plurality of CCD shift registers, which are arranged in succession to the respective shift registers of the image pickup portion
1
i
, and wherein the number of bits corresponds to the respective shift registers. The bits of these shift registers temporarily store respective information charges that are transferred out from the pixels of the image pickup portion
1
i
. The horizontal transfer section
1
h
comprises a single CCD shift register, the bits of which are connected to the outputs of the shift registers of the storage portion
1
s
. The information charges, which are transferred one horizontal line at a time from the storage portion
1
s
, are transferred in sequence to the output section
1
d
. The output section
1
d
comprises a capacitance for receiving information charges and is provided at the output side of the horizontal transfer section
1
h
. The output section
1
d
, the capacitance of which receives information charges that are transferred out from the horizontal transfer section
1
h
, outputs voltage values proportional to the charge amounts. Changes in the voltage values that are output become an image signal Y
0
(t).
A drive circuit
2
comprises a frame clock generator portion
2
f
, a vertical clock generator portion
2
v
, a horizontal clock generator portion
2
h
, a reset clock generator portion
2
r
, and a sampling clock generator portion
2
s
. The frame clock generator portion
2
f
generates in response to a frame shift timing signal FT a frame clock &phgr;f for supply to the image pickup portion
1
i
. The information charges that have accumulated in the pixels of the image pickup portion
1
i
are transferred at a high speed to the storage portion
1
s
each vertical scanning period. The vertical clock generator portion
2
v
generates a vertical clock &phgr;v for the storage portion
1
s
in response to a vertical synchronization signal VT and a horizontal synchronization signal HT. As a result, as the information charges that are transferred out from the image pickup portion
1
i
are captured and temporarily stored, and the stored information charges are then transferred one horizontal line at a time to the horizontal transfer section
1
h
during each horizontal scanning period. The horizontal clock generator portion
2
h
generates in response to the horizontal synchronization signal HT a horizontal transfer clock &phgr;h for supply to the horizontal transfer section
1
h
. As a result, the information charges that were captured one horizontal line at a time in the horizontal transfer section
1
h
from the storage portion
1
s
are transferred in sequence to the output section
1
d
. The reset clock generator portion
2
r
generates, in synchronization with the operation of the horizontal clock generator portion
2
h
, a reset clock &phgr;r for supply to the output section
1
d
for discharging the information charges that are stored in the capacitance of the output section
1
d
. As a result, the information charges that are output from the horizontal transfer section
1
h
to the output section
1
d
are stored in the capacitance of the output section
1
d
in one pixel units. The sampling clock generator portion
2
s
, similar to the reset clock generator portion
2
r
, then generates a sampling clock &phgr;s for supply to a sample-and-hold circuit
4
in synchronization with the operation of the horizontal clock generator portion
2
h
for sequentially sampling the image signal Y
0
(t).
A timing control circuit
3
operates based on a reference clock CLK having a fixed period, and generates the vertical synchronization signal VT and horizontal synchronization signal HT, which determine the respective timing of the vertical scanning and horizontal scanning of the image sensor
1
, for supply to the drive circuit
2
. The timing control circuit
3
also generates the frame shift timing signal FT at a period coinciding with the vertical synchronization signal VT for supply to the drive circuit
2
. The timing control circuit
3
performs shutter control to discharge the information charges of the image pickup portion
1
i
during the vertical scanning period corresponding to the amount of information charges generated at the image pickup portion
1
i
in order to maintain an optimum light exposure state of the image sensor
1
. In other words, when the timing of the shutter operation is made faster, the period lengthens from the start of accumulation of the information charges until the start of frame transfer, and the accumulation of information charges is performed for a longer period at image pickup portion
1
i
. Conversely, when the timing of the shutter operation is made slower, the period shortens from the start of accumulation of the information charges until the start of frame transfer, and the accumulation of information charges is performed for a short period at image pickup portion
1
i
. The shutter operation for discharging the information charges of the image pickup portion
1
i
is accomplished through the action of a drive clock, which is supplied from the drive circuit
2
to the image sensor
1
.
The sample-and-hold circuit
4
generates the image signal Y
1
(t) for maintaining signal levels by sampling the image signal Y
0
(t) in response to the sampling clock &phgr;s supplied from the sampling clock generator portion
2
s
. Normally, since charging and discharging of the capacitance in the output section
1
d
repeat according to reset clock &phgr;r, a reset level and a signal level, which corresponds to the information charge amount, alternately repeat in the image signal Y
0
(t) that is obtained from the output section
1
d
. The phase of the sampling clock &phgr;s is set so that only the signal level is extracted within the image signal Y
0
(t). Therefore, the image signal Y
1
(t), in which only the signal levels corresponding to the information charge amounts stored in output section
1
d
follow in succession, can be obtained.
A divider circuit
5
divides the reset clock &phgr;r and sampling clock &phgr;s as necessary so that information charges for multiple pixels can be mixed at the output section
1
d
by setting the reset operation of the output section
1
d
to be intermittent. As shown in
FIG. 3
, the divider circuit
5
may be composed, for example, so as to divide by two the reset clock &phgr;r and sampling clock &phgr;s that are generated in the same period as the horizontal clock &phgr;h, and supply a reset clock &phgr;r 0 and a sampling clock &phgr;s
0
, which
Christensen Andrew
Hogan & Hartson LLP
Sanyo Electric Co,. Ltd.
Wisdahl Eric
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