Shift register

Details Shift register Shift register

1999-08-27

2003-04-29

Lam, Tuan T. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Using shift register

C377S064000, C377S075000

Reexamination Certificate

active

06556646

ABSTRACT:

This application claims the benefit of Korean Patent Application No. P98-44180, filed on Oct. 21, 1998.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a circuit for driving a display device of active matrix type, and more particularly to a shift register for driving pixel rows in a liquid crystal display.
2. Description of the Prior Art
Generally, a conventional liquid crystal display device used in a television or a computer includes a liquid crystal matrix having liquid crystal cells arranged at intersections of data lines and select or gate lines. The select lines are horizontal lines (i.e., row lines) of the liquid crystal matrix, which are sequentially driven with a shift register. As shown in
FIG. 1
, the conventional shift register includes n stages
2
1
to
2
n
connected in cascade and simultaneously connected, via output lines to
4
1
to
4
n
, to n row lines ROW
1
to ROWn or gate lines, respectively. A scanning pulse SP is inputted to the first stage
2
1
, and output signals g
1
to g
n−1
of the previous stages are inputted to the 2nd to nth stages
2
2
to
2
n
, respectively. Also, n stages
2
1
to
2
n
receive two clock signals out of three clock signals C
1
to C
3
. Each of the n stages
2
1
to
2
n
drives an associated row line ROWi connected to a pixel train with the two clock signals and the output signals of previous stages or with the two clock signals and the scanning pulse SP.
As shown in
FIG. 2
, each of the stages
2
1
to
2
n
includes a fifth NMOS transistor T
5
for applying a high logic voltage signal to an output line
4
i
, and a sixth NMOS transistor T
6
for applying a low logic voltage signal to the output line
4
i
. If a high logic level of (i−1)th row line input signal g
i−1
is applied from the previous stage
2
i−1
, then first and fourth NMOS transistors T
1
and T
4
are turned on. As seen from
FIG. 3
, a high logic level of third clock signal C
3
is synchronized with the (i−1)th row line input signal g
i−1
and applied to a third NMOS transistor T
3
, thereby turning on the third NMOS transistor T
3
. The third and fourth NMOS transistors T
3
and T
4
are a so-called ‘ratioed logic’ which are set to an appropriate ratio of resistance values in such a manner that a voltage at a second node P
2
becomes a low level when the third and fourth NMOS transistors T
3
and T
4
are simultaneously turned on. Accordingly, when (i−1)th row line input signal g
i−1
is applied, a low logic level voltage emerges at the second node P
2
. At this time, the second and sixth NMOS transistor T
2
and T
6
are turned off by a low logic level voltage from the second node P
2
. A first node P
1
is charged into a high logic level voltage by a supply voltage VDD when the first NMOS transistor T
1
is turned on and the second NMOS transistor T
2
is turned off When the high logic level voltage at the first node P
1
arrives at a threshold voltage thereof, the fifth NMOS transistor T
5
is turned off. At this time, since the first clock signal C
1
remains at a low logic level, a low logic level voltage emerges at the output line
4
i
.
If the first clock signal C
1
has a high logic level voltage during a time interval when a voltage at the first node P
1
remains at a high logic level, then the output line
4
i
becomes a high logic level by a high logic level first clock signal C
1
applied via the fifth NMOS transistor T
5
. Accordingly, a high logic level output signal Vout emerges at the output line
4
i
. At this time, since the output line
4
i
and the first node P
1
are coupled as shown in
FIG. 4
with a parasitic capacitance Cgs existing between the gate and the source of the fifth NMOS transistor T
5
, a voltage at the first node P
1
is bootstrapped into a high logic voltage level. Accordingly, the high logic level voltage of the first clock signal C
1
is applied to the output line
4
i
almost without a loss. Such a bootstrap system is used to compensate a voltage loss caused by a threshold voltage generated at a circuit including NMOS transistors.
Also, if the first clock signal C
1
is changed from a high logic level voltage into a low logic level voltage, a voltage Vout at the output line
4
i
drops into a low logic level voltage because the fifth NMOS transistor T
5
is in a turned-off state. Furthermore, since the first and fourth NMOS transistors T
1
and T
4
are turned off by the (i−1)th row line input signal gin having a low logic level voltage in such a manner to be supplied with no voltage, a voltage level at the first node P
1
also drops slowly. In such a state, if the third clock signal C
3
has a high logic level voltage, then the third NMOS transistor T
3
is turned off to thereby begin charging the second node P
2
into a high logic level voltage with the aid of the supply voltage VDD applied via the third NMOS transistor T
3
. The sixth NMOS transistor T
6
is turned on by a voltage signal higher than its threshold voltage applied from the second node P
2
to discharge a voltage charged on the output line
4
i
toward a ground voltage VSS. As a result, a voltage at the row line ROWi connected to the output line
4
i
maintains a low logic level.
In order to operate such a shift register normally, a resistance ratio of the third and fourth NMOS transistors T
3
and T
4
serving as a ratioed logic must be set accurately. In other words, in order to generate a low logic level voltage at the second node P
2
when the third clock signal C
3
having a high level voltage and the (i−1)th row line input signal g
i−1
are applied simultaneously to the gates of the third and fourth NMOS transistors T
3
and T
4
, a channel width of the fourth NMOS transistor T
4
must be about ten times larger than that of the third NMOS transistor T
3
. If characteristics of the NMOS transistors T
3
and T
4
become non-uniform, a current ratio of the third NMOS transistor T
3
to the fourth NMOS transistor T
4
varies. In this case, the shift register fails to operate properly.
Further, since a direct current flows continuously at the third and fourth NMOS transistors T
3
and T
4
when the third and fourth NMOS transistors T
3
and T
4
are simultaneously turned on by the third clock signal C
3
and the (i−1)th row line input signal g
i−1
, the characteristics of the third and fourth NMOS transistors T
3
and T
4
are susceptible to deterioration by overcurrent. Also, if the first clock signal C
1
is changed from a low logic level voltage into a high logic level voltage during an interval when a voltage at the first node P
1
is in a state of high logic level, then a rising width in a bootstrapped voltage at the first node P
1
becomes different in accordance with a parasitic capacitance value of the fifth NMOS transistor T
5
and a change in the parasitic capacitance at the first node P
1
. The voltage rising width at the first node P
1
is as described in the following formula (1):
Δ
⁢
 
⁢
Vp1
=
CAP
+
C
OX
C
L1
+
CAP
+
C
OX
⁢
Δ
⁢
 
⁢
Vout
(
1
)
wherein &Dgr;Vp
1
and &Dgr;Vout represent a voltage change amount at the first node P
1
and a voltage change amount at the output line
4
i
, respectively, and C
L
and C
ox
represents a parasitic capacitance at the first node P
1
and a parasitic capacitance of the fifth NMOS transistor T
5
, respectively. The parasitic capacitance C
ox
of the fifth NMOS transistor T
5
is equal to a sum of parasitic capacitance Cgs between the gate and the source thereof and parasitic capacitance Cds between the drain and the gate thereof.
As seen from the formula (1), since a rising width in a voltage at the first node P
1
is changed by the capacitance C
L
at the first node P
1
and the parasitic capacitance C
ox
of the fifth NMOS transistor T
5
, it is difficult to set a characteristic of shift register accurately. Moreover, in the shift register of
FIG. 2
, the output voltage Vout at the output line
4
i
is distorted because a voltage at the seco

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