Semiconductor memory device and information processing unit

Details Semiconductor memory device and information processing unit Semiconductor memory device and information processing unit

2001-11-09

2003-04-08

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230030, C365S230060

Reexamination Certificate

active

06545942

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor memory device and information processing unit and, more particularly, to a semiconductor memory device having a burst mode, in which a plurality of bits of data are consecutively transferred in block in response to an external command, and information processing unit having such a semiconductor memory device.
2. Description of the Related Art
(First Prior Art)
With what is called an I/O common semiconductor memory device in which written data and read data flow along the same data bus, the data bus can be used effectively by setting write latency, being delay time between the inputting of a write command and the writing of data to be written.
FIG. 34
is a timing chart showing how to transfer data in the case of write latency not being set.
FIG. 35
is a timing chart showing how to transfer data in the case of write latency being set.
FIG. 34
is a view showing a read-write-read (RD-WR-RD) cycle in the case of burst length being “2” and write latency being “0.” In this example, an RD command is input in synchronization with the leading edge of the zeroth clock (CLK) shown in FIG.
34
(A) (see FIG.
34
(B)). With most semiconductor memory devices, certain access time is needed between the inputting of an RD command (CMD) and the sending of data to a bus. In this example, as shown in FIG.
34
(C), bits of read data (DATA) Q
1
and Q
2
are sent to a data bus at the leading edge of the third clock, that is to say, when three clocks have elapsed after the inputting of the RD command.
After the bits of read data are sent, a WR command is input at the leading edge of the fifth clock. The write latency is “0,” so bits of written data D
1
and D
2
are input via the data bus almost concurrently with the inputting of the WR command.
The following RD command is input directly after the WR command, because there exists a delay corresponding to access time between the inputting of an RD command and the sending of data to the data bus and the data bus will not be congested with written data and read data.
As stated above, if the write latency is set to “0,” RD—RD cycle time from an RD command to the next RD command is six clocks.
FIG. 35
is a view showing an RD-WR-RD cycle in the case of burst length being “2” and write latency being “3.” In this example, an RD command is input in synchronization with the leading edge of the zeroth clock shown in FIG.
35
(A) (see FIG.
35
(B)). As stated above, with a semiconductor memory device, certain access time is needed between the inputting of an RD command and the sending of data to a bus. In this example, the bits of read data Q
1
and Q
2
are sent to the data bus at the leading edge of the third clock (see FIG.
35
(C)).
If write latency is set, there exists a delay between the inputting of a WR command and the inputting of written data. A WR command therefore can be read prior to the sending of read data. In this example, a WR command is input at the leading edge of the second clock.
After the WR command is input and clocks corresponding to the write latency (three clocks, in this example) have elapsed, written data is read. In this example, the bits of written data D
1
and D
2
are read at the leading edge of the fifth clock.
The following RD command is input directly after the WR command, because, as stated above, there exists a delay corresponding to access time between the inputting of an RD command and the sending of data to the data bus and the data bus will not be congested with written data and read data. Read data corresponding to this RD command is read at the leading edge of the sixth clock.
As described above, if the write latency is set to “3,” RD—RD cycle time from an RD command to the next RD command is three clocks. As a result, RD—RD cycle time can be shortened by three clocks in comparison to the above case where the write latency is set to “0.”
(Second Prior Art)
Bank interleaving is one of techniques for realizing high-speed access to a semiconductor memory device.
With the bank interleaving technique, the whole of a memory is divided into a plurality of banks and is managed. When a CPU begins to access one of the banks, it begins to access another bank to be accessed next. By the time the first access by the CPU ends, the bank accessed next by the CPU is in a state in which data can already be transferred. The CPU therefore can transfer data without delay.
FIG. 36
is a timing chart showing operation for conventional bank interleaving.
FIG. 37
is a view showing an example of circuits for realizing such bank interleaving.
A CLK (clock) input terminal
201
shown in
FIG. 37
receives a CLK signal input from the outside. A CMD (command) input terminal
202
receives a CMD signal input from the outside. An ADD (address) input terminal
203
receives an ADD signal input from the outside.
A CLK input circuit
204
provides the CLK signal input from the CLK input terminal
201
to a CMD input circuit
205
, ADD input circuit
206
, and burst length counter
209
.
The CMD input circuit
205
performs waveform shaping on the CMD signal input from the CMD input terminal
202
and provides it to a CMD decoder
207
.
The ADD input circuit
206
performs waveform shaping on the ADD signal input from the ADD input terminal
203
and provides it to a burst length judging circuit
208
, burst address generating circuit
210
, and address importing circuit
211
.
The CMD decoder
207
decodes the CMD signal, extracts an RD (read) command, WR (write) command, and NOP (no operation) command from it, and provides them to the burst length counter
209
and address importing circuit
211
.
If a command for setting a burst length is input at the time of, for example, starting a device, the burst length judging circuit
208
analyzes the command and judges the set burst length.
When the RD command or WR command is input and a burst transfer is begun, the burst length counter
209
resets the burst address generating circuit
210
, counts the burst length in response to the CLK signal, and requests the burst address generating circuit
210
to count up a burst address. Furthermore, when the count reaches the burst length, the burst length counter
209
requests the burst address generating circuit
210
to end generating the burst address.
The address importing circuit
211
refers to the CMD signal supplied from the CMD decoder
207
and, at the time of the burst transfer being begun, selects the ADD signal supplied from the ADD input circuit
206
to output it as an internal address IADD. Furthermore, in order to transfer the second bit and the following lower-order bits, the address importing circuit
211
selects output from the burst address generating circuit
210
and outputs it as the internal address IADD.
Now, operation for the above conventional bank interleaving will be described with reference to FIG.
36
.
It is assumed that a device is started, that an MRS (mode register set) command for setting a burst length is input to the CMD input terminal
202
, and that data showing the burst length to be set is input to the ADD input terminal
203
. Then the CMD decoder
207
recognizes that a request to set the burst length was made and informs the burst length judging circuit
208
of it.
The burst length judging circuit
208
refers to data supplied from the ADD input circuit
206
and judges the burst length to be set. For example, if a request to set a burst length to “4” is made, the burst length judging circuit
208
recognizes it and informs the burst length counter
209
of it. As a result, the setting of burst length will be completed.
In this state of things, it is assumed that an RD
1
command to request a burst transfer with a predetermined bank as a target (see FIG.
36
(B)) is input to the CMD input terminal
202
at the zeroth leading edge of a CLK signal shown in FIG.
36
(A). Then the CMD decoder
207
receives this signal via the CMD input circuit
205
, recognizes that an RD command was input, and informs the burst lengt

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