Method of manufacturing non-volatile semiconductor memory...

Details Method of manufacturing non-volatile semiconductor memory... Method of manufacturing non-volatile semiconductor memory...

2002-06-21

2003-07-22

Meier, Stephen D. (Department: 2825)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S425000, C438S426000, C438S359000, C438S699000

Reexamination Certificate

active

06596608

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for producing a nonvolatile semiconductor memory device. More specifically, the invention relates to a method for producing a non-volatile semiconductor memory device in which trenches in a memory cell region and trenches in other regions having a depth different from the depth of the trench in the memory cell region are formed in a reduced number of processes.
BACKGROUND OF THE INVENTION
Large-scale integration of a semiconductor device that uses a silicon substrate is realized by providing a device isolating region between a plurality of transistors. As the device isolating regions used in the semiconductor device, there are a P-N junction isolating region, a LOCOS (local Oxidation of Silicon)-type field insulating film, and a trench isolating region. P-N junction isolating regions and trench isolating regions become device isolating regions for such devices as those in a collector region of a bipolar transistor having a deep P-N junction. The field insulating film, on the other hand, becomes a device isolating region between devices formed on the silicon substrate and wires provided on the silicon substrate, or a device isolating region for such devices as those in a source/drain regions of a MOS transistor having a shallow P-N junction.
The field insulating film has been employed for a device isolating region for a semiconductor device that comprises MOS transistors, and the field insulating film and either one of the P-N junction isolating region and the trench isolating region have been employed as a device isolating region for a semiconductor device that comprises bipolar transistors. With a progress of device miniaturization, special emphasis is placed on a self-alignment technique, and reduced size of a device isolating region are also pursued. Thus, in the semiconductor device that comprises the MOS transistors, an LOCOS-type field insulating film has become mainstream, while in the semiconductor device that comprises bipolar transistors, a combined use of the LOCOS-type field insulating film and the trench isolating region has become mainstream.
In the semiconductor device that comprises the MOS transistors, P-channel MOS transistors were mainly used at first. However, N-channel MOS transistors came into use, and now CMOS transistors have been mainly used. In a semiconductor device comprising the CMOS transistors, either one of an N well or a P well was employed. Recently, both N and P wells, that is, twin wells are employed. For this reason, even in the semiconductor device that comprises MOS transistors, a device isolating region for N and P wells having the deep P-N junction becomes necessary. In addition, use of a trench isolating region has begun to be studied as a measure against latch-up. Further, a BiCMOS transistor that comprises a CMOS transistor and a bipolar transistor has been spotlighted, so that the importance of the device isolating region that comprises a LOCOS-type field oxide film and a trench isolating region has increased.
Next, device isolating structures in a conventional non-volatile semiconductor device will be described with reference to a drawing. Referring to
FIG. 18
d
, the non-volatile semiconductor device comprises a memory cell region
20
, a device isolating region
21
, and a peripheral circuit region
22
. In the memory cell region
20
, there is provided between cells device a device isolator
8
a
filled into a trench that penetrates through a first silicon oxide film
3
and extends into a silicon substrate
1
. In the device isolating region
21
, there is provided a field oxide film
2
formed on the surface of the silicon substrate
1
by a LOCOS process and a device isolator
8
b
filled into a trench that penetrates through the field oxide film
2
and extends into the silicon substrate
1
. In the peripheral circuit region
22
, there is provided between transistors a device isolator
8
c
which has been filled into a trench that penetrates through the first silicon oxide film
3
and extends into the silicon substrate
1
. Generally, a silicon oxide film is employed for the device isolators
8
a
,
8
b
and
8
c.
A conventional typical method for producing the device isolators will be described.
The field oxide film
2
and the first silicon oxide film
3
that becomes a first gate insulating film are formed on the silicon substrate
1
by the LOCOS and thermal oxidation processes. Then, a silicon nitride film
6
is formed on the field oxide film
2
and the first silicon oxide film
3
. Thereafter, a resist
7
for forming trenches in the respective regions is formed (see
FIG. 18
a
).
Next, in the respective regions, the trenches having the same depth from an interface between the silicon substrate
1
and the field oxide film
2
and from an interface between the silicon substrate
1
and the first silicon oxide film
3
are formed (see
FIG. 18
b
).
Then, after removing the resist
7
, the trenches are filled with insulating films such as a silicon oxide film. The device isolators
8
a
,
8
b
and
8
c
are thereby formed.
Then, the silicon oxide film
3
is removed from the peripheral circuit region
22
to form a p-well
30
, and then a gate insulation film
32
is selectively formed on the surface of the peripheral circuit region
22
. Thereafter, floating gates
4
are formed on the memory cell region (see
FIG. 18
c
).
Next, an ONO film
9
is selectively formed on the floating gates
4
, and then control gates
10
a
are formed on the memory cell region, and gates
10
b
and
10
c
are formed on the peripheral circuit region.
An N-type diffusion layer
31
that becomes source/drain regions are formed with respect to the gates
10
b
and
10
c
on the peripheral circuit region (see
FIG. 18
d
). With this arrangement, a source/drain region associated with the gate
10
b
and a source/drain region associated with the gate
10
c
are isolated by the device isolator
8
c.
SUMMARY OF THE DISCLOSURE
Forming of trenches in the respective regions with the same depth from the interface between the silicon substrate
1
and the field oxide film
2
and from the interface between the silicon substrate
1
and the first silicon oxide film
3
in the above-mentioned way, results in the following problems.
The device isolators
8
a
that achieve isolation between memory devices on the memory cell region
20
and the device isolator
8
c
that achieves isolation between source/drain regions for adjacent transistors on the peripheral circuit region
22
have optimum depths, respectively. Since an impurity diffusion region that becomes source wiring is formed under the trenches filled with the device isolators
8
a
, the depth of the device isolator
8
a
cannot be made to be so deep.
On the other hand, if the depth of the device isolator
8
c
is shallow, a parasitic bipolar transistor is formed between the source and the drain of adjacent transistors, so that so-called latch-up may occur. Thus, the depth of the device isolator
8
c
cannot be made to be so shallow.
In other words, if the depth of the source/drain regions for the transistors become close to the depth of the device isolator
8
c
, the parasitic effects of an npn bipolar transistor arise, where a source/drain region
31
between the adjacent transistors is made to be an emitter and a collector, and the p-well
30
is made to be a base. Thus, it is necessary for the device isolator
8
c
to have a depth just sufficient for ensuring isolation of the source/drain regions
31
.
In short, if the depth of the device isolator
8
c
is adjusted to the depth required for the device isolators
8
a
, latch-up might occur in the peripheral circuit region
22
.
On the contrary, if the depth of the device isolators
8
a
is adjusted to the depth required for the device isolator
8
c
, formation of source wiring under the trenches filled with the device isolators
8
a
becomes difficult.
In order to solve the problems described above, separate formation of trenches in the respective regions can be conceived.

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